High voltage swing output buffer in low voltage technology

• US 5,808,480 A
• Filed: 02/29/1996
• Issued: 09/15/1998
• Est. Priority Date: 02/29/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Morris, Bernard Lee
• Primary Examiner(s): SANTAMAURO, JON P
• Application Number:
  US08/607,954
• Time in Patent Office: 929 Days
• Field of Search: 326/68, 326/80-81, 326/83, 326/63, 326/121, 326/86, 327/333, 327/544
• US Class Current: 326/81
• CPC Class Codes: H03K 19/018521 of complementary type, e.g. CMOS

Abstract

An integrated circuit output buffer that is fabricated using a relatively low voltage technology is capable of driving a relatively high voltage swing to an output conductor. For example, a buffer implemented in 3.3 volt CMOS technology can deliver a 5 volt output swing. This is achieved by scaling up the output voltage swings from the lower voltage level to the higher voltage level using one or more intermediate inverters that operate at successively higher voltage levels. In a preferred embodiment, the voltage levels are provided using a power conservation circuit that limits current flow through a resistor voltage divider network.

Claims

1. An integrated circuit comprising an output buffer implemented in a relatively low voltage technology and adapted to deliver a relatively high voltage output swing,

characterized in that said output buffer comprises a buffer input inverter operating at a low power supply voltage and having an output, a buffer output inverter operating at a high power supply voltage and having an input, and at least one intermediate inverter having an input coupled to the output of said buffer input inverter and having an output coupled to the input of said buffer output inverter and operating at an intermediate power supply voltage greater that said low power supply voltage but less than said high power supply voltage, wherein said intermediate voltage is obtained from a voltage divider network connected to said high power supply voltage, with said voltage divider network comprising a series string of voltage divider resistors, and wherein said voltage divider network further comprises at least one switching device for reducing the current flowing through said resistor string during a lower power mode.

2. The integrated circuit of claim 1 wherein said buffer input inverter, said buffer output inverter, and said at least one intermediate inverter each comprise a p-channel pull-up transistor and an n-channel pull-down transistor.

3. The integrated circuit of claim 1 wherein said low voltage technology is limited to a said low voltage by at least one factor selected from the group consisting of:

gate-to-source breakdown voltage, gate-to-drain breakdown voltage, and source-to-drain voltage limit.

4. The integrated circuit of claim 1 wherein said low voltage technology is nominally 3.3 volts or less.

5. An integrated circuit comprising an output buffer having transistors with gate, source, and drain electrodes implemented in a given technology, with said output buffer adapted to deliver an output signal at a voltage greater than that which would cause degradation in the reliability of said transistors if said voltage were applied across two of said electrodes of any one of said transistors,

characterized in that said output buffer comprises an input inverter having an output coupled to an input of a first intermediate inverter having an output coupled to an input of an output inverter,

and wherein said input inverter operates at a low power supply voltage, said output inverter operates at a high power supply voltage, and said first intermediate inverter operates at a first intermediate power supply voltage greater than said low power supply voltage but less than said high power supply voltage.

6. The integrated circuit of claim 5 further comprising at least one additional intermediate inverter having an input coupled to the output of said first intermediate inverter, an output coupled to the input of said output inverter, and operating at a second intermediate power supply voltage greater than said first intermediate power supply voltage but less than said high power supply voltage.

7. The integrated circuit of claim 5 wherein said first intermediate voltage is obtained from voltage divider network connected to said high power supply voltage.

8. The integrated circuit of claim 7 wherein said voltage divider network comprises a series string of voltage divider resistors.

9. The integrated circuit of claim 8 wherein said voltage divider network further comprises at least one switching device for reducing the current flowing through said resistor string during a low power mode.

10. The integrated circuit of claim 5 wherein said buffer input inverter, said buffer output inverter, and said at least one intermediate inverter each comprise a p-channel pull-up transistor and an n-channel pull-down transistor.

11. The integrated circuit of claim 5 wherein said low voltage technology is limited to a said low voltage by at least one factor selected from the group consisting of:

gate-to-source breakdown voltage, gate-to-drain breakdown voltage, and source-to-drain voltage limit.

12. The integrated circuit of claim 5 wherein said low voltage technology is nominally 3.3 volts or less.