Logic circuit utilizing pass transistors and logic gate

• US 5,808,483 A
• Filed: 09/20/1996
• Issued: 09/15/1998
• Est. Priority Date: 09/22/1995
• Status: Expired due to Term

• Current Assignee: Kawasaki Microelectronics Incorporated (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated)
• Inventors: Sako, Norimitsu
• Primary Examiner(s): Westin, Edward P.
• Assistant Examiner(s): ROSEEN, RICHARD R
• Application Number:
  US08/716,883
• Time in Patent Office: 725 Days
• Field of Search: 326/113, 326/121, 326/21, 326/104
• US Class Current: 326/113
• CPC Class Codes: H03K 19/1737 using multiplexers H03K19/1738 takes precedence

Abstract

A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.

Claims

1. A logic circuit comprising:

at least two pass-transistor logic trees each comprising at least two pass transistors and having at least two input nodes for receiving input logic signals and an intermediate output node for providing an intermediate logic signal;

a multiple-input complementary logic gate having at least two intermediate input nodes each for receiving the intermediate logic signal from corresponding one of the at least two pass-transistor logic trees, and an output node for providing an output logic signal; and

a suppressor of a static feedthrough current of the multiple-input complementary logic gate.

2. The logic circuit according to claim 1, wherein said complementary logic gate is a CMOS logic gate.

3. The logic circuit according to claim 1, wherein said suppressor of static feedthrough current comprises means for restoring potentials of the intermediate output nodes of the pass transistor logic trees.

4. The logic circuit according to claim 3, wherein said means for restoring restores the potentials of the intermediate output nodes to at least approximately one of a reference potential and a power supply potential.

5. The logic circuit according to claim 3, wherein said means for restoring restores the potentials of the intermediate output nodes of all the pass-transistor logic trees only when logic states of the intermediate logic signals of all the pass-transistor logic trees are the same.

6. The logic circuit according to claim 3, wherein said means for restoring restores the potentials of the intermediate output nodes of all the pass-transistor logic trees in response to the output logic signal of the multiple-input complementary logic gate.

7. The logic circuit according to claim 6, wherein said multiple-input complementary logic gate is one of an AND, an OR, a NAND and a NOR gate.

8. The logic circuit according to claim 6, wherein

each of the pass transistors comprises an N channel MOS transistor and said multiple-input complementary logic gate is a CMOS NAND gate;

and

said means for restoring pulls up the potentials of all the intermediate output nodes of all the pass-transistor logic trees to at least approximately a power supply potential when the output logic signal of the CMOS NAND gate is in a LOW state.

9. The logic circuit according to claim 8, wherein

said means for restoring includes P channel MOS transistors each provided for each of the pass-transistor logic trees;

and

each of the P channel MOS transistors has a gate terminal for receiving the output logic signal of the CMOS NAND gate, a drain terminal connected to the intermediate output node of the corresponding pass-transistor logic tree, and a source terminal for receiving the power supply potential.

10. The logic circuit according to claim 3, wherein

each of the pass transistors comprises a switching device having a first conduction type and a first driving capacity, and having an input, an output and a control terminal;

and

said means for restoring comprises auxiliary switching devices, each provided for each of the switching devices, each of the auxiliary switching devices having a second conduction type and a second driving capacity which is less than the first driving capacity;

wherein each of the auxiliary switching devices having an input terminal connected to the input terminal of the corresponding switching device, an output terminal connected to the output terminal of the corresponding switching device, and a control terminal for receiving a complementary logic signal of a logic signal received by the control terminal of the corresponding switching device.

11. The logic circuit according to claim 10, wherein the second driving capacity is less than about 1/3 of the first driving capacity.

12. The logic circuit according to claim 10, wherein the second driving capacity is not greater then about 1/6 of the first driving capacity.

13. The logic circuit according to claim 10, wherein the second driving capacity is not greater than about 1/15 of the first driving capacity.

14. The logic circuit according to claim 10, wherein said switching devices are N channel MOS transistors each having a first W/L ratio, and the auxiliary switching devices are P channel MOS transistors each having a second W/L ratio which is less than the first W/L ratio.

15. The logic circuit according to claim 14, wherein the second W/L ratio is not larger than about 1/2 of that of the first W/L ratio.

16. The logic circuit according to claim 14, wherein the second W/L ratio is not larger than about 1/5 of that of the first W/L ratio.

17. The integrated circuit device according to claim 10, wherein

each of the pass transistors has an input, an output and a control terminal;

and

each of the pass-transistor logic trees comprises at least one pair pass transistor element each including a first and a second pass transistor selected from the at least two pass transistors, the output terminals of the pass transistors in each of the at least one pair pass transistor element being coupled.

18. The integrated circuit device according to claim 17, wherein said switching devices are N channel MOS transistors each having a first W/L ratio, and the auxiliary switching devices are P channel MOS transistors each having a second W/L ratio which is less than the first W/L ratio.

19. The integrated circuit device according to claim 18, wherein the control terminal of the auxiliary switching device in the second pass transistor is connected to the control terminal of the switching device in the first pass transistor, and the control terminal of the auxiliary switching device in the first pass transistor is connected to the control terminal of the switching device in the second pass transistor.

20. The logic circuit according to claim 2, wherein

each of the pass transistors comprises a first conduction type switching device having a first threshold voltage;

and

said suppressor comprises second conduction type switching devices which constitute the multiple-input CMOS logic gate, each of the second conduction type switching devices having a second threshold voltage;

wherein an absolute value of the second threshold voltage is higher than an absolute value of the first threshold voltage.

21. The logic circuit according to claim 20, wherein said first conduction type switching devices are N channel MOS transistors, and said second conduction type switching devices are P channel MOS transistors.

22. The logic circuit according to claim 21, wherein difference between the absolute value of the second threshold voltage and the absolute value of the first threshold voltage is not less than about 0.7V.

23. A logic circuit comprising:

at least two pass-transistor logic trees each comprising at least two pass transistors and having at least two input nodes for receiving input logic signals and an intermediate output node for providing an intermediate logic signal, each of the pass transistors comprising a switching device having a first conduction type and a first driving capacity, and having an input, an output and a control terminal; and

a multiple-input logic gate having at least two intermediate input nodes each for receiving the intermediate logic signal from corresponding one of the at least two pass-transistor logic trees, and an output node for providing an output logic signal;

wherein each of the pass transistors further comprises auxiliary switching devices each provided for each of the switching devices, each of the auxiliary switching devices having a second conduction type and a second driving capacity which is less than the first driving capacity; and

each of the auxiliary switching devices having an input terminal connected to the input terminal of the corresponding switching device, an output terminal connected to the output terminal of the corresponding switching device, and a control terminal for receiving a complementary logic signal of a logic signal received by the control terminal of the corresponding switching device.

24. The logic circuit according to claim 23, wherein the second driving capacity is less than about 1/3 of the first driving capacity.

25. The logic circuit according to claim 23, wherein the second driving capacity is not greater than about 1/6 of the first driving capacity.

26. The logic circuit according to claim 23, wherein the second driving capacity is not greater than about 1/15 of the first driving capacity.

27. The logic circuit according to claim 23, wherein said multiple-input logic gate is a multiple-input complementary logic gate.

28. The logic circuit according to claim 27, wherein the second driving capacity is less than about 1/3 of the first driving capacity.

29. The logic circuit according to claim 27, wherein the second driving capacity is not greater than about 1/6 of the first driving capacity.

30. The logic circuit according to claim 27, wherein the second driving capacity is not greater than about 1/15 of the first-driving capacity.

31. The logic circuit according to claim 27, wherein said complementary logic gate is a CMOS logic gate.

32. The logic circuit according to claim 31, wherein said switching devices are N channel MOS transistors each having a first W/L ratio, and the auxiliary switching devices are P channel MOS transistors each having a second W/L ratio which is less than the first W/L ratio.

33. The logic circuit according to claim 32, wherein the second W/L ratio is not greater than about 1/2 of that of the first W/L ratio.

34. The logic circuit according to claim 33, wherein the second W/L ratio is not greater than about 1/5 of that of the W/L ratio.

35. The logic circuit according to claim 31, wherein

each of the pass transistors has an input, an output and a control terminal;

and

each of the pass-transistor logic trees comprises at least one pair of pass transistor elements each comprising a first and a second pass transistor selected from the at least two pass transistors, the output terminals of the pass transistors in each of the at least one pair pass transistor element being coupled.

36. The logic circuit according to claim 35, wherein said switching devices are N channel MOS transistors each having a first W/L ratio, and the auxiliary switching devices are P channel MOS transistors each having a second W/L ratio which is less than the first W/L ratio.

37. The logic circuit according to claim 36, wherein the control terminal of the auxiliary switching device in the second pass transistor is connected to the control terminal of the switching device in the first pass transistor, and the control terminal of the auxiliary switching device in the first pass transistor is connected to the control terminal of the switching device in the second pass transistor.