Logic circuit utilizing pass transistors and logic gate
First Claim
1. A logic circuit comprising:
- at least two pass-transistor logic trees each comprising at least two pass transistors and having at least two input nodes for receiving input logic signals and an intermediate output node for providing an intermediate logic signal;
a multiple-input complementary logic gate having at least two intermediate input nodes each for receiving the intermediate logic signal from corresponding one of the at least two pass-transistor logic trees, and an output node for providing an output logic signal; and
a suppressor of a static feedthrough current of the multiple-input complementary logic gate.
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Abstract
A logic circuit combines a plurality of pass-transistor logic trees and a multiple-input logic gate for receiving intermediate logic signals from the respective pass-transistor logic trees, and can express a complex logical operation while decreasing the number of stages in pass-transistor logic trees and improving operation speed. Even a logical operation that cannot be expressed efficiently by a known or conventional pass-transistor logic circuit can be expressed efficiently with performance higher than that of a known CMOS logic circuit. Furthermore, when a static feedthrough current of the multiple-input logic gate is suppressed, power consumption can be reduced. In some embodiments, since circuitry for suppressing a static feedthrough current of the multiple-input logic gate is arranged so that a probability of occurrence of logical collision with a preceding stage will decrease or will be nil, power consumption can further be reduced.
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Citations
37 Claims
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1. A logic circuit comprising:
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at least two pass-transistor logic trees each comprising at least two pass transistors and having at least two input nodes for receiving input logic signals and an intermediate output node for providing an intermediate logic signal; a multiple-input complementary logic gate having at least two intermediate input nodes each for receiving the intermediate logic signal from corresponding one of the at least two pass-transistor logic trees, and an output node for providing an output logic signal; and a suppressor of a static feedthrough current of the multiple-input complementary logic gate. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22)
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23. A logic circuit comprising:
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at least two pass-transistor logic trees each comprising at least two pass transistors and having at least two input nodes for receiving input logic signals and an intermediate output node for providing an intermediate logic signal, each of the pass transistors comprising a switching device having a first conduction type and a first driving capacity, and having an input, an output and a control terminal; and a multiple-input logic gate having at least two intermediate input nodes each for receiving the intermediate logic signal from corresponding one of the at least two pass-transistor logic trees, and an output node for providing an output logic signal; wherein each of the pass transistors further comprises auxiliary switching devices each provided for each of the switching devices, each of the auxiliary switching devices having a second conduction type and a second driving capacity which is less than the first driving capacity; and each of the auxiliary switching devices having an input terminal connected to the input terminal of the corresponding switching device, an output terminal connected to the output terminal of the corresponding switching device, and a control terminal for receiving a complementary logic signal of a logic signal received by the control terminal of the corresponding switching device. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36, 37)
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Specification