Rail-to-rail input common mode range differential amplifier that operates with very low rail-to-rail voltages

• US 5,808,513 A
• Filed: 12/10/1997
• Issued: 09/15/1998
• Est. Priority Date: 08/23/1995
• Status: Expired due to Term

• Current Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Original Assignee: National Semiconductor Corporation (Texas Instruments, Inc.)
• Inventors: Archer, Donald M.
• Primary Examiner(s): Mullins, James B.
• Application Number:
  US08/988,346
• Time in Patent Office: 279 Days
• Field of Search: 330/252, 330/253, 330/258, 330/311
• US Class Current: 330/253
• CPC Class Codes: H03F 2203/45371 the AAC comprising parallel coupled multiple transistors at their source and gate and drain or at their base and emitter and collector, e.g. in a cascode dif amp, only those forming the composite common source transistor or the composite common emitter transistor respectively
• CPC Class Codes: H03F 2203/45676 the LC comprising one cascode current mirror
• CPC Class Codes: H03F 3/45192 Folded cascode stages
• CPC Class Codes: H03F 3/45479 characterised by the way of common mode signal rejection
• CPC Class Codes: H03F 3/45632 in differential amplifiers with FET transistors as the active amplifying circuit H03F3/4578 takes precedence

Abstract

A rail-to-rail input common mode range differential amplifier operates on rail-to-rail voltages down to approximately one volt by utilizing one p-channel transistor to cover a first portion of the common mode range, and a second p-channel transistor to cover a second portion of the common mode range.

Claims

1. A rail-to-rail input common mode range differential amplifier for amplifying a voltage difference between a pair of differential inputs, the amplifier comprising:

a current source stage that outputs first and second tail currents; and

a differential pair stage that receives the first and second tail currents, outputs first and second intermediate currents, and varies the magnitude of the first and second intermediate currents in response to the voltage difference between the differential inputs; and

wherein the differential pair stage includes a first pair of MOS transistors of a first conductivity type connected to the current source stage to receive the first tail current, and to the pair of differential inputs such that a first MOS transistor of the first pair of MOS transistors is connected to the first differential input and a second MOS transistor of the first pair of MOS transistors is connected to the second differential input, the first pair of transistors outputting the first and second intermediate currents when the voltages on the first and second differential inputs are in a first voltage range; and

wherein the differential pair stage includes a second pair of MOS transistors of the first conductivity type connected to the current source stage to receive the second tail current, and to the pair of differential inputs such that a first MOS transistor of the second pair of MOS transistors is connected to the first differential input and a second MOS transistor of the second pair of MOS transistors is connected to the second differential input, the second pair of MOS transistors outputting the first and second intermediate currents when the voltages on the first and second differential inputs are in a second voltage range; and

wherein the first pair of MOS transistors have a first threshold voltage, and

wherein the second pair of MOS transistors have a second threshold voltage different from the first threshold voltage.

2. A rail-to-rail input common mode range differential amplifier for amplifying a voltage difference between a pair of differential inputs, the amplifier comprising:

a current source stage that outputs first and second tail currents; and

a differential pair stage that receives the first and second tail currents, outputs first and second intermediate currents, and varies the magnitude of the first and second intermediate currents in response to the voltage difference between the differential inputs; and

wherein the differential pair stage includes a first pair of n-channel transistors connected to the current source stage to receive the first tail current, and to the pair of differential inputs such that a first transistor of the first pair of transistors is connected to the first differential input and a second transistor of the first pair of transistors is connected to the second differential input, the first pair of transistors outputting the first and second intermediate currents when the voltages on the first and second differential inputs are in a first voltage range; and

wherein the differential pair stage includes a second pair of n-channel transistors connected to the current source stage to receive the second tail current, and to the pair of differential inputs such that a first transistor of the second pair of transistors is connected to the first differential input and a second transistor of the second pair of transistors is connected to the second differential input, the second pair of transistors outputting the first and second intermediate currents when the voltages on the first and second differential inputs are in a second voltage range; and

wherein the first pair of transistors have a first threshold voltage, and

wherein the second pair of transistors have a second threshold voltage different from the first threshold voltage.

3. A rail-to-rail input common mode range differential amplifier as in claim 2, and wherein the first pair of transistors are enhancement-type MOS transistors and the second pair of transistors are depletion-type MOS transistors.