Resistor string digital-to-analog converter

• US 5,808,576 A
• Filed: 02/24/1997
• Issued: 09/15/1998
• Est. Priority Date: 02/24/1997
• Status: Expired due to Term

• Current Assignee: Texas Instruments, Inc.
• Original Assignee: Texas Instruments, Inc.
• Inventors: Chloupek, James, Yang, Steve Wiyi, Yung, Henry Tin-Hang
• Primary Examiner(s): Hoff, Marc S.
• Application Number:
  US08/804,559
• Time in Patent Office: 568 Days
• Field of Search: 341/144, 341/154, 341/153
• US Class Current: 341/144
• CPC Class Codes: H03M 1/687 Segmented, i.e. the more significant bit converter being of the unary decoded type and the less significant bit converter being of the binary weighted type
• CPC Class Codes: H03M 1/765 using a single level of switches which are controlled by unary decoded digital signals
• CPC Class Codes: H03M 1/808 using resistors

Abstract

A digital-to-analog converter includes a first array of resistors 10-16 connected in series; a switch matrix 20 coupled to the first array of resistors 10-16; a first variable resistor RTOP coupled to a first end of the first array of resistors 10-16; and a second variable resistor RBOT coupled to a second end of the first array of resistors 10-16, the first variable resistor RTOP and the second variable resistor RBOT having a combined resistance that is a fixed resistance value.

Claims

1. A digital-to-analog converter comprising:

a first array of resistors connected in series;

a switch matrix coupled to the first array of resistors;

a first variable resistor coupled to a first end of the first array of resistors, the first variable resistor has resistance values ranging from (1/N times R) to R in increments of (1/N times R) . where R is a fixed resistance value and N is an integer greater than two; and

a second variable resistor coupled to a second end of the first array of resistors, the second variable resistor has resistance values ranging from (/N times R) to zero in decrements of (1/N times R), the first variable resistor and the second variable resistor having a combined resistance of R.

2. The device of claim 1 wherein all resistors in the first array of resistors have a resistance value of R.

3. The device of claim 1 wherein the first variable resistor comprises;

a second array of resistors connected in series; and

a first array of switches coupled to the second array of resistors, a first end of each switch in the first array of switches is coupled to a first end of a corresponding resistor in the second array of resistors, a second end of each switch is coupled to a first reference node.

4. The device of claim 3 wherein the second variable resistor comprises:

a third array of resistors connected in series; and

a second array of switches coupled to the third array of resistors, a first end of each switch in the second array of switches is coupled to a first end of a corresponding resistor in the third array of resistors, a second end of each switch is coupled to a second reference node.

5. The device of claim 4 wherein the third array of resistors has one less resistor than the second array of resistors.

6. The device of claim 1 wherein the first variable resistor comprises:

a second array of resistors connected in series;

an operational amplifier having an output coupled to a first end of the second array of resistors; and

,

a first array of switches, a first end of each switch in the first array of switches is coupled to a first end of a corresponding resistor in the second array of resistors, a second end of each switch in the first array of switches is coupled to a first input of the operational amplifier, a second input of the operational amplifier is coupled to a reference node.

7. The device of claim 6 further comprising a second array of switches, a first end of each switch in the second array of switches is coupled to the first end of the corresponding resistor in the second array of resistors, a second end of each switch in the second array of switches is coupled to the output of the operational amplifier.

8. The device of claim 1 wherein the second variable resistor comprises;

a second array of resistors coupled in series, a first resistor in the second array of resistors having a first resistance value and a second resistor having a second resistance value;

a first switch, a first end of the first switch is coupled to a first end of the first resistor, a second end of the first switch is coupled to a reference node;

a second switch, a first end of the second switch is coupled to the reference node, a second end of the second switch is coupled to a second end of the first resistor;

a third switch, a first end of the third switch is coupled to the second end of the first resistor, a second end of the third switch is coupled to a first end of the second resistor; and

,

a fourth switch, a first end of the fourth switch is coupled to the second end of the first resistor, a second end of the fourth switch is coupled to a second end of the second resistor.