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Reconfiguring control system in a parallel processing system by replacing an error-detected processing unit

  • US 5,808,886 A
  • Filed: 03/14/1995
  • Issued: 09/15/1998
  • Est. Priority Date: 03/17/1994
  • Status: Expired due to Fees
First Claim
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1. A communication control method for a parallel processing system having a plurality of processor units which are connected with a network through network routers for data transfer to be carried out by transmission and reception of packets between said processor units, comprising:

  • a processor address translation table in which correspondence between logical addresses and physical addresses of said processor units is provided in a certain specific processor unit of said plurality of processor units or a monitor processor which is separately provided to monitor a condition of said parallel processing system;

    a packet sending processor unit for transmitting a packet to which its own processor unit address and a logical address as a receiver processor unit address are added;

    a network router for receiving said packet, generating a request to said monitor processor to obtain a physical address corresponding to a logical address of a receiver processor unit and selecting a route of the network in accordance with said physical address, wherein a certain specific processor unit in which a fault occurs is logically separated from the network by changing the correspondence between the logical addresses and the physical addresses of the processor address translation table and a processor unit is selected as the substitute processor unit from a plurality of valid processors indicated in the processor address translation table, each network router is provided with a receiver address table in which correspondence between identification bits which indicate whether or not a processor unit connected to said network router is receiving and processing packets and logical addresses of sender processor units of said packets is registered, and the monitor processor reads the receiver address table of a network router connected to the fault-detected processor unit when a fault occurs in the receiver processor unit and, if one of said identification bits indicates that the processor unit is receiving and processing packets, informs resuming of packet transmission to the packet sending processor unit of the corresponding logical address.

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