Diagnostic system

• US 5,808,919 A
• Filed: 10/31/1995
• Issued: 09/15/1998
• Est. Priority Date: 11/23/1993
• Status: Expired due to Term

• Current Assignee: Keysight Technologies, Inc.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Preist, Christopher William, Allport, David
• Primary Examiner(s): Voeltz, Emanuel T.
• Assistant Examiner(s): ASSOUAD, PATRICK J
• Application Number:
  US08/551,054
• Time in Patent Office: 1,050 Days
• Field of Search: 364/578, 364/579, 364/580, 371/22.1, 371/22.4, 371/22.6, 371/25.1, 371/26
• US Class Current: 702/183
• CPC Class Codes: G01R 31/00 Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere measuring superconductive properties G01R33/1238; testing or measuring semiconductors or solid state devices during manufacture H01L22/00; testing line transmission systems H04B3/46
• CPC Class Codes: G01R 31/31912 Tester/user interface
• CPC Class Codes: G06F 11/2205 using arrangements specific to the hardware being tested

Abstract

A diagnostic system (10) for diagnosing the cause of failures of functional tests made on a system under test wherein the system under test comprises a plurality of interacting components and wherein the diagnostic system (10) comprises means (20) for interpreting test results based on the set of operations which are involved in carrying out the tests and which components are exercised by operations.

Claims

1. A diagnostic system for diagnosing a cause of failures of functional tests made on a system under test wherein the system under test includes a plurality of interacting components and wherein the diagnostic system comprises:

memory means for storing data regarding the components of the system under test wherein data regarding connectivity of components is not necessary, data regarding test results, and data regarding the functional tests applied to the system under test, including information about which operations are performed in the system under test during a functional test and which components are involved in said operations; and

means coupled to said memory means and responsive to data stored therein, for determining sets of components that are logically possible causes of test failures.

2. A diagnostic system according to claim 1 further comprising means for computing a weight for each logically possible cause of failures, and determining a most likely diagnosis based on the weights, said weights based on the degree to which operations utilise the components in the system under test.

3. A diagnostic system according to claim 2 which is operable to recognise when an operation is involved in both failing and passing tests (an `operation violation`) and wherein said means for computing a weight alters the weight assigned to a particular component when the particular component is utilized in no failing tests other than in tests involved in operation violations.

4. A diagnostic system according to claim 3 which is operable to apply a penalty factor to each candidate diagnosis (D) involving operation violations.

5. A diagnostic system according to claim 1, further comprising:

means for providing a list of each candidate diagnosis (D), ranked in order of probability.

6. A diagnostic system according to claim 1 comprising:

means for indicating further tests which could usefully be carried out following a diagnosis.

7. A diagnostic system according claim 1 which is integrated with a functional test system so that it further comprises:

means for storing test definitions;

means for performing tests on the system under test;

means for storing test results;

and wherein the diagnostic system is operable automatically to utilize the test results to diagnose causes of test failures.

8. A diagnostic system according to claim 1 which is operable to utilize the results of individual component tests generated prior to the system under test.

9. A diagnostic system according to claim 1 operable to diagnose faults in printed circuit boards or multi-chip modules.