Semiconductor memory device having a defect relief arrangement

• US 5,808,944 A
• Filed: 01/31/1997
• Issued: 09/15/1998
• Est. Priority Date: 02/08/1996
• Status: Expired due to Term

• Current Assignee: Renesas Electronics Corporation
• Original Assignee: Hitachi, Ltd., Hitachi ULSI Engineering Corp, Mitsubishi Denki Kabushiki Kaisha (Mitsubishi Electric Corporation)
• Inventors: Tanaka, Shigeru, Ohba, Atsushi, Nakamura, Yasuhiro, Miyazawa, Kazuyuki, Tanaka, Toshihiro, Oshima, Kazuyoshi, Yoshitake, Takayuki
• Primary Examiner(s): ZARABIAN, AMIR
• Application Number:
  US08/797,654
• Time in Patent Office: 592 Days
• Field of Search: 365/200, 365/96, 365/236, 365/185.09
• US Class Current: 365/200
• CPC Class Codes: G11C 29/80 with improved layout

Abstract

In a semiconductor storage device wherein data lines connected to a plurality of memory cells selected by a select operation of word lines are sequentially selected by using an address signal generated by an address counter to serially read data in individual unit of at least one word line: redundancy data lines disposed perpendicular to the word lines are provided; a column select circuit receiving a Y address signal selects one of the data lines or redundancy data lines; a redundancy memory circuit stores, in the order of the selection operation by the column select circuit, a defect address signal of a defect data line among the data lines and a redundancy address signal of a corresponding redundancy data line; an address comparator circuit compares one defect address signal read from the redundancy memory circuit with an address signal generated by the address counter; an address signal for the redundancy memory circuit is generated by performing a count operation in response to a coincidence signal generated by the address comparator circuit; and the address signal generated by the address counter is replaced by a redundancy address signal read in response to the coincidence signal from the redundancy memory circuit and used as the Y address signal. Accordingly, a redundancy circuit of simple configuration can be obtained because only a single address comparator circuit is used.

Claims

1. A semiconductor memory device comprising:

a normal memory array having a plurality of memory cells disposed in a matrix, each memory cell being disposed at each cross point between a plurality of word lines and a plurality of data lines;

a redundancy array having a plurality of redundancy memory cells disposed in a matrix, each redundancy memory cell being disposed at each cross point between the plurality of word lines and a plurality of redundancy data lines;

an address counter for generating an address signal which selects one of the data lines of said normal memory array;

a column select circuit for selecting one of the data lines in said normal memory array or in said redundancy memory array in accordance with a Y address signal;

a redundancy memory circuit for storing, in the order of a selection operation by said column select circuit, a defect signal of a defect data line of said normal memory array and a redundancy address signal assigned to said redundancy array;

an address comparator circuit for comparing one defect address signal read from said redundancy memory circuit with an address signal generated by said address counter;

a redundancy address counter performing a count operation in response to a coincidence signal from said address comparator circuit and generating an address signal for reading a next defect address signal from said redundancy memory circuit; and

a redundancy address select circuit responsive to the address signal generated by said redundancy address counter for reading one defect address signal and its corresponding redundancy address signal from said redundancy memory circuit,

wherein in response to the coincidence signal from said address comparator circuit, the address signal generated by said address counter is replaced by the redundancy address signal read from said redundancy memory circuit to use the redundancy address signal as the Y address signal.

2. A semiconductor memory device according to claim 1, wherein said redundancy memory circuit stores as the redundancy address signal an address signal having only lower bits corresponding to the number of redundancy data lines of said redundancy array, and the upper bits assigned to said redundancy array are fixedly set at the outside of said redundancy memory circuit and added to the lower bits to form the Y address signal.

3. A semiconductor memory device according to claim 1, further comprising a management array having a plurality of data lines for management bits crossing the plurality of word lines, wherein the redundancy data line of the redundancy array is used also for relieving a detect data line for the management bit.

4. A semiconductor memory device according to claim 1, wherein said redundancy memory circuit uses, as a memory cell, fuse means capable of being selectively blown out by application of a laser beam.

5. A semiconductor memory device according to claim 1, wherein the memory cells are electrically erasable and programmable non-volatile memory cells capable of being collectively erased in individual units of a word line.

6. A semiconductor memory device according to claim 1, wherein a combination of a control signal and a clock signal is used and a command for designating an operation mode and an X address signal for selecting one of the word lines are time divisionally input from a data terminal.