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Time division multiplexed synchronous state machine having state memory

  • US 5,809,032 A
  • Filed: 01/15/1997
  • Issued: 09/15/1998
  • Est. Priority Date: 05/21/1992
  • Status: Expired due to Term
First Claim
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1. A receive SONET line interface, comprising:

  • a pointer tracking circuit (122), responsive to a SONET signal (108) and a previous state pointer tracking signal (129c), for providing a data signal (118a) at a line clock (110) rate and for providing a next state pointer tracking signal (129a);

    a line side state memory (126), responsive to said next state pointer tracking signal (129a) and to a line side write address signal, for storing said next state pointer tracking signal (129a) for a selected period and responsive to a line side read address signal (126b), for providing said previous state pointer tracking signal (129c) after said selected period;

    an elastic store (102), responsive to said data signal at said line clock rate and to an elastic store write address signal (102a), for storing said data signal (118a) and responsive to an elastic store read address signal (102b), for providing a data signal (120a) at a local clock (114) rate;

    a pointer generating circuit (124), responsive to said data signal (120a) at a local clock rate and responsive to a previous state pointer generating signal (129d), for providing a data signal (121a) having pointer value and adjustments and a next state pointer generating signal (129b); and

    a local side state memory (128), responsive to said next state pointer generating signal (129b) and to a write address signal (128a), for storing said next state pointer generating signal (129b) for said selected period and responsive to a local side read address signal (128b), for providing said previous state pointer generating signal (129d).

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