Commonly housed multiple processor type computing system and method of manufacturing the same

• US 5,809,262 A
• Filed: 08/30/1996
• Issued: 09/15/1998
• Est. Priority Date: 05/17/1995
• Status: Expired due to Term

• Current Assignee: Dell USA LP (Dell Technologies Inc.)
• Original Assignee: Dell USA LP (Dell Technologies Inc.)
• Inventors: Potter, Bruce
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): DHARIA, RUPAL
• Application Number:
  US08/706,001
• Time in Patent Office: 746 Days
• Field of Search: 395/306, 395/309, 395/308, 395/310
• US Class Current: 710/305
• CPC Class Codes: G06F 13/387 for adaptation of different data processing systems to different peripheral devices, e.g. protocol converters for incompatible systems, open system
• CPC Class Codes: G06F 13/4027 using bus bridges G06F13/4022 takes precedence

Abstract

A multiple processor type computing system and an associated method of manufacturing the same from first and second computer systems, each of which include a PCI bus and both a processor and LAN device coupled to the PCI bus, which are selected such that the processors of the computer systems are configured to execute software utilizing different operating systems. Each LAN device is installed on the PCI bus using a PCI interface and is comprised of a data register, a data FIFO and a LAN controller coupled together using internal circuitry. Also coupled to the internal circuitry is a serial I/O port used to connect the LAN device to a network. From these, a multiple processor computing system is manufactured by removing the serial I/O port from each of the LAN devices to expose the internal circuitry thereof. The internal circuitry of the LAN devices are then interconnected to couple the first and second processors in a single multiple processor computing system which is supportably mounted in a common computer chassis. The data register and data FIFO of the first LAN device holds selected address, data and control signals during transfers from the first processor to the second processor arranged by the LAN controller of the first LAN device while the data register and data FIFO of the second LAN device holds selected address, data and control signals during transfers from the second processor to the first processor arranged by the LAN controller of the second LAN device.

Claims

1. A multiple processor type computing system, comprising:

a first PCI bus;

a first processor subsystem coupled to said first PCI bus;

a second PCI bus;

a second processor subsystem coupled to said second PCI bus;

a first PCI interface coupled to said first PCI bus;

a second PCI interface coupled to said second PCI bus;

an interface device coupled to said first PCI bus interface and said second PCI bus interface;

a first memory device coupled to said interface device, said first PCI interface and said second PCI interface, said first memory device holding address, data and control signals from said first processor subsystem to be transferred to said second processor subsystem; and

a second memory device coupled to said interface device, said first PCI interface and said second PCI interface, said second memory device holding address, data and control signals from said second processor subsystem to be transferred to said first processor subsystem,

wherein said interface device includes a controller circuit for transferring address, data and control signals placed in said first memory device by said first processor subsystem to said second processor subsystem and for transferring address, data and control signals placed in said second memory device by said second processor subsystem to said first processor subsystem.

2. A multiple processor computing system according to claim 1 wherein said interface device further comprises:

a controller circuit coupled to said first PCI interface, said second PCI interface, said first memory device and said second memory device, said controller circuit arranging the transfer of address, data and control signals placed in said first memory device by said first processor subsystem to said second processor subsystem and the transfer of address, data and control signals placed in said second memory device by said second processor subsystem to said first processor subsystem.

3. A multiple processor computing system according to claim 1 wherein said first memory device is a first data register and said second memory device is a second data register.

4. A multiple processor computing system according to claim 1 wherein said first memory device is a first data FIFO and said second memory device is a second data FIFO.

5. A multiple processor computing system according to claim 1 wherein said first memory device is a first data register holding selected ones of address, data and control signals being transferred from said first processor subsystem to said second processor subsystem, wherein said second memory device is a second data register holding selected ones of address, data and control signals being transferred from said second processor subsystem to said first processor subsystem, and wherein said interface device further comprises:

a first data FIFO coupled to said first and second PCI interfaces, said first data FIFO holding remaining ones of address, data and control signals being transferred from said first processor subsystem to said second processor subsystem; and

a second data FIFO coupled to said first and second PCI interfaces, said second data FIFO holding remaining ones of address, data and control signals being transferred from said second processor subsystem to said first processor subsystem.

6. A method of manufacturing a multiple processor computer system having a first processor and a second processor, comprising the steps of:

providing a first computer system having a first PCI bus, a first processor coupled to said first PCI bus and a first LAN device coupled to said first PCI bus, said first LAN device interconnected with a network, internal logic, and at least one internal connector coupled to said internal logic;

providing a second computer system having a second PCI bus, a second processor coupled to said second PCI bus and a second LAN device coupled to said second PCI bus, said second LAN device interconnected with a network, internal logic and at least one internal connector coupled to said internal logic;

interconnecting said at least one connector of said first LAN device with said at least one connector interconnected with said second LAN device to couple said first computer system with said second computer system as a multiple processor computing system.

7. A method of manufacturing a multiple processor computing system according to claim 6 wherein said first processor is configured to execute software which utilizes a first operating system and said second processor is configured to execute software which utilizes a second operating system.

8. A method of manufacturing a multiple processor computing system according to claim 7 and further comprising the steps of:

providing a computer chassis; and

supportably mounting said first computer system and said second computer system within said computer chassis.

9. A method of manufacturing a multiple processor computer system according to claim 8 and further comprising the steps of:

providing a peripheral device; and

coupling said peripheral device to said first PCI bus;

wherein said peripheral device may be used by both said first processor and said second processor.