Integrated circuit I/O using a high performance bus interface
First Claim
1. A memory subsystem for storing and retrieving data, comprising:
- (1) at least one memory device that includes a bus interface, the memory device having at least one memory section comprised of a plurality of memory cells; and
(2) a bus, wherein the bus interface of the at least one memory device couples the memory device to the bus, wherein the bus comprises a group of controlled impedance transmission lines for carrying substantially all information necessary for a single memory device to receive a transaction request, including a memory transaction request, and for carrying substantially all information necessary for a single memory device to respond to the transaction request;
wherein the number of signaling lines is substantially less than the number of bits in the information necessary to request a memory transaction to store or retrieve data from the memory cells; and
wherein memory device selection information is time-multiplexed on the bus with other memory transaction request information.
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Accused Products
Abstract
A memory subsystem for storing and retrieving data. At least one memory device Includes a bus Interface. The memory device has at least one memory section comprised of a plurality of memory cells. The bus interface of the at least one memory device couples the memory device to a bus. The bus comprises a group of controlled impedance transmission lines for carrying substantially all information necessary for a single memory device to receive a transaction request, including a memory transaction request, and for carrying substantially all information necessary for a single memory device to respond to the transaction request. The number of signaling lines is substantially less than the number of bits in the information necessary to request a memory transaction to store or retrieve data from the memory cells. Memory device selection information is time-multiplexed on the bus with other memory transaction request information.
171 Citations
57 Claims
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1. A memory subsystem for storing and retrieving data, comprising:
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(1) at least one memory device that includes a bus interface, the memory device having at least one memory section comprised of a plurality of memory cells; and (2) a bus, wherein the bus interface of the at least one memory device couples the memory device to the bus, wherein the bus comprises a group of controlled impedance transmission lines for carrying substantially all information necessary for a single memory device to receive a transaction request, including a memory transaction request, and for carrying substantially all information necessary for a single memory device to respond to the transaction request; wherein the number of signaling lines is substantially less than the number of bits in the information necessary to request a memory transaction to store or retrieve data from the memory cells; and wherein memory device selection information is time-multiplexed on the bus with other memory transaction request information. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of communicating over a bus in a memory subsystem, the method comprising the steps of:
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(1) a master transmitting on the bus a transaction request, wherein the bus comprises a group of signaling lines that carry substantially all information necessary for a single memory device to receive a transaction request, including a memory transaction request, wherein the signaling lines carry substantially all Information necessary for a single memory device to respond to the transaction request, and wherein the number of signaling lines is substantially less than the number of bits in the memory transaction request; wherein memory device selection information is time-multiplexed on the bus with other memory transaction request information; (2) the memory device receiving the transaction request transmitted on the signaling lines; (3) the memory device determining whether it should respond to the transaction request; and (4) if the memory device has determined that it should respond to the transaction request, then the memory device responding to the transaction request by receiving data information sent by the master on the signaling lines when receiving data information is necessary to perform a first type of transaction indicated in the transaction request, or by transmitting data information to the master on the signaling lines when transmitting data information is necessary to perform a second type of transaction indicated in the transaction request. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22, 23, 24)
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25. A memory device, comprising:
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(1) at least one memory section comprised of a plurality of memory cells; (2) a bus interface for coupling the memory section to a bus having a group of signaling lines, wherein the number of signaling lines is substantially less than the number of bits in the information necessary to request a memory transaction to store or retrieve data from the memory cells; wherein the signaling lines carry substantially all information necessary for a single memory device to receive the memory transaction request; wherein the signaling lines carry substantially all information necessary for a single memory device to respond to the memory transaction request; wherein memory device selection information is time-multiplexed on the bus with other memory transaction request information; and wherein the signaling lines comprise controlled impedance transmission lines. - View Dependent Claims (26, 27)
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28. An apparatus comprising:
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(1) at least two semiconductor devices; (2) a group of signaling lines to which the semiconductor devices are coupled, wherein the number of signaling lines is substantially less than the number of bits in the information necessary to request a transaction to be performed by a single semiconductor device, wherein the signaling lines carry substantially all information necessary for a single semiconductor device to receive the transaction request, wherein the signaling lines carry substantially all information necessary for a single semiconductor device to respond to the transaction request, wherein the signaling lines comprise transmission lines having substantially the same electrical characteristics and the transmission lines are of a controlled impedance, wherein the signals on the signaling lines are created from current source drivers; and (3) at least one clock line for transmission a pair of clock signals to be received by the semiconductor devices, wherein the clock signals have a clock rate a short cycle time, and a clock cycle having a first phase and a second phase, wherein information necessary to request and to respond to a transaction is placed on the group of signaling lines in response to the start of the first phase, and wherein information necessary to request and to respond to a transaction is placed on the group of signaling lines in response to the start of the second phase so that a data information rate is twice the clock rate.
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29. An apparatus for storing and retrieving data, the apparatus comprising:
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(1) a multiline bus for transmitting address information, control information, and data, wherein the multiline bus has a total number of lines less than a total number of bits in any single address and wherein the control information includes information for selecting memories; (2) a master coupled to the multiline bus for (A) initiating a read operation by placing on the multiline bus a read request packet comprising (i) read control information comprising a read device identifier, a read cycle type, and a maximum data transfer length indicator and (ii) read address information comprising a read starting address, and for (B) initiating a write operation by placing on the multiline bus a (i) write request packet comprising (a) write control information comprising a write device identifier and a write cycle type and (b) write address information comprising a write starting address and (ii) write data (3) a first memory coupled to the multiline bus for responding to the read request packet from the master by placing onto the multiline bus data returned from a location within the first memory beginning at the read starting address if the read identifier matches an identifier of the first memory; (4) a second memory coupled to the multiline bus for responding to the write request packet from the master by storing in the second memory at the write starting address the write data if the write device identifier matches an identifier of the second memory. - View Dependent Claims (30, 31, 32)
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33. An apparatus for high-speed access to blocks of data according to a synchronous, split transaction, block-oriented protocol, the apparatus comprising:
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(1) a multiline bus for transmitting address information, control information, and blocks of data, wherein the multiline bus has a total number of lines less than the total number of bits in a single address, wherein the control information includes information for selecting memories; (2) a clock running at a clock rate; (3) a master coupled to the clock and to the multiline bus for (A) initiating a clocked read operation of a first block of data by placing on the multiline bus a read request packet comprising read address and control information and for (B) initiating a clocked write operation of a second block of data by placing on the multiline bus a (I) write request packet comprising write address and control information and the (ii) second block of data; (4) a first memory coupled to the clock and to the multiline bus for responding to the read request packet from the master by placing onto the multiline bus in a clocked manner the first block of data returned from a location within the first memory if the read request packet identifies the first memory; (5) a second memory coupled to the clock and to the multiline bus for responding to the write request packet from the master by storing in the second memory the second block of data received from the multiline bus in a clocked manner if the write request packet identifies the second memory.
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34. An apparatus for high-bandwidth data transfer, the apparatus comprising:
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(1) a multiline bus for transmitting address information, control information, and data, wherein the control information includes information for selecting memories without the use of dedicated memory select lines; (2) a master coupled to the multiline bus for initiating a read operation by placing on the multiline bus a read request packet and for initiating a write operation by placing on the multiline bus a write request packet followed by write data; (3) a first memory coupled to the multiline bus via bus interface built into the first memory and residing on a single edge of the first memory, wherein the first memory responds to the read request packet from the master by placing on the multiline bus data returned from a location within the first memory if the read request packet identifies the first memory; (4) a second memory coupled to the multiline bus via a bus interface built into the second memory and residing on a single edge of the second memory, wherein the second memory responds to the write request packet from the master by storing in the second memory data received from the multiline bus if the write request packet identifies the second memory. - View Dependent Claims (35)
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36. A method for retrieving data, comprising the steps of:
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(1) having a master initiate a read operation by placing onto a multiline bus a read request packet comprising a read device identifier, a read cycle type, a maximum transfer length indicator, and a read starting address; (2) having a first memory of a plurality of memories coupled to the multiline bus respond to the read request packet from the master by placing onto the multiline bus data returned from a location within the first memory beginning at the read starting address if the read device identifier matches an identifier of the first memory.
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37. A method for storing data, comprising the steps of:
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(1) having a master initiate a write operation by placing onto a multiline bus (A) a write request packet comprising write device identifier, a write cycle type, and a write starting address and (B) write data; and (2) having a first memory of a plurality of memories coupled to the multiline bus respond to the write request packet from the master by storing in the first memory at the write starting address the write data if the write device identifier matches an identifier of the first memory. - View Dependent Claims (38)
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39. A method for storing and retrieving data, comprising the steps of:
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(1) having a master attempt a read operation by placing onto a multiline bus a read request packet comprising a read device identifier, a read cycle type, a maximum transfer length indicator, and a read starting address; (2) having the master attempt a write operation by placing onto a multiline bus (A) a write request packet comprising a write device identifier, a write cycle type, and a write starting address and (B) write data; (3) if the read device identifier or write device identifier matches an identifier of a first memory of a plurality of memories coupled to the multiline bus and the first memory cannot respond to the read request packet or the write request packet, then having the first memory place onto the multiline bus a retry message request that the master retry a request.
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40. An apparatus for high-bandwidth data transfer, the apparatus comprising:
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(1) a multiline bus for transmitting address information, control information, and data, wherein the multiline bus has a total number of lines less than a total number of bits in any single address, wherein the control information includes information for selecting memories; (2) a master coupled to the multiline bus for (A) initiating a read operation by placing on the multiline bus a read request packet comprising read address and control information and for (B) initiating a write operation by placing on the multiline bus (i) a write request packet comprising write address and control information and (ii) write data; (3) a first memory coupled to the multiline bus for responding to the read request packet from the master by placing onto the multiline bus data returned from a location within the first memory if the read request packet identifies the first memory; (4) a second memory coupled to the multiline bus for responding to the write request packet from the master by storing in the second memory data received from the multiline bus if the write request packet identifies the second memory; and (5) timing circuitry for ensuring that the first memory places data onto the multiline bus at a predetermined time.
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41. An apparatus comprising;
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(1) a master coupled to a bus for initiating a response by placing on the bus a request packet; and (2) a slave coupled to the bus, wherein the slave includes an access-time register that stores a value that determines a timing of a response by the slave to the request packet. - View Dependent Claims (42, 43)
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44. An apparatus comprising:
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(1) a slave coupled to a bus, wherein the slave includes a plurality of selectable access-time registers storing a plurality of timing values, wherein a timing value stored by an access-time register selected from the plurality of access-time registers determines a timing of a response by the slave to a request packet; (2) a master coupled to a bus for initiating the response by the slave by placing on the bus the request packet, wherein the request packet includes code for selecting one of the plurality of access-time registers. - View Dependent Claims (45, 46)
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47. A memory device, comprising:
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(1) at least one memory section comprised of a plurality of memory cells; (2) a bus interface for coupling the memory section to a bus comprised a group of signaling lines, wherein the number of signaling lines is substantially less than the number of bits in a memory transaction request to store or retrieve data from the memory cells; wherein the signaling lines carry substantially all Information necessary for a single memory device to receive the memory transaction request; wherein the signaling lines carry substantially all information necessary for a single memory device to respond to the memory transaction request; wherein substantially all information necessary for a single memory device to receive the memory transaction request includes address information and control information; wherein the control information includes memory device selection information; and wherein the control information is time multiplexed with the address information over the group of signaling lines.
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48. A method of communicating over a bus to a memory device, the bus comprising a group of signaling lines, the method comprising the steps of:
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(1) a master transmitting on the bus a transaction request, the bus carrying substantially all address, data, and control information needed by the memory device to receive and respond to the transaction request and having substantially fewer signaling lines than the number of bits in the address information, the control information including memory device selection information and being time-multiplexed with address information over the group of signaling lines; (2) the memory device receiving the transaction request transmitted on the signaling lines; and (3) the memory device responding to the received transaction request according to the information in the transaction request.
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49. An apparatus comprising:
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(1) at least two semiconductor devices, each having a bus interface; and (2) a bidirectional bus comprising a group of signaling lines and coupling to the bus Interfaces of the semiconductor devices, wherein the number of signaling lines is substantially less than the number of bits in the information necessary for one device to request a transaction to be performed by the other device, wherein the signaling lines carry substantially all information necessary for the semiconductor device to receive and respond to the transaction request, and wherein the transaction request includes device selection information time-multiplexed on the bus with other transaction request information.
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50. A memory device comprising:
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at least one memory section comprised of a plurality of memory cells; a synchronous bus interface coupling the memory section to a bus comprising a group of signaling lines, the synchronous bus interface having an input coupled to receive an external clock signal and receiving a transaction request on the bus synchronously with the external clock signal, the synchronous bus interface receiving or transferring data information on the bus synchronously with the external clock signal in response to the transaction request; and wherein the bus carries substantially all address, data, and control information needed by the memory device to receive and respond to the transaction request and the bus has substantially fewer bus lines than the number of bits in the address information. - View Dependent Claims (51)
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52. A memory device comprising:
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at least one dynamic memory section comprised of a plurality of memory cells; and a synchronous bus interface coupling the memory section to a bus comprising a group of signaling lines, the synchronous bus interface having an input coupled to receive an external clock signal, wherein the interface receives control and address Information on the bus synchronously with the external clock signal, the control information being time-multiplexed with address information over the group of signaling lines and wherein the bus has substantially fewer bus lines than the number of bits in the address information. - View Dependent Claims (53, 54, 55, 56)
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57. An apparatus comprising:
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at least two semiconductor devices each having a bus interface; and a bidirectional bus comprising a group of signaling lines and coupling to the bus interfaces of the semiconductor devices; wherein the number of signaling lines is substantially less than the number of bits in the information necessary for one device to request a transaction to be performed by the other device; wherein the signaling lines carry substantially all information necessary for the semiconductor device to receive and respond to the transaction request; and wherein the transaction request includes device selection information time-multiplexed on the bus with other transaction request information.
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Specification