Inverse quantizer

• US 5,809,270 A
• Filed: 09/25/1997
• Issued: 09/15/1998
• Est. Priority Date: 06/30/1992
• Status: Expired due to Term

• Current Assignee: Coases Investments Bros LLC (Intellectual Ventures LLC)
• Original Assignee: Discovision Associates (Pioneer Corporation)
• Inventors: Robbins, William Philip
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/947,727
• Time in Patent Office: 355 Days
• Field of Search: 395/376, 395/800.01, 348/409, 348/384
• US Class Current: 712/200
• CPC Class Codes: G06F 12/0207 with multidimensional access, e.g. row/column, matrix
• CPC Class Codes: G06F 12/04 Addressing variable-length words or parts of words
• CPC Class Codes: G06F 12/0607 Interleaved addressing
• CPC Class Codes: G06F 13/16 for access to memory bus G06F13/28 takes precedence
• CPC Class Codes: G06F 13/28 using burst mode transfer, e.g. direct memory access DMA, cycle steal G06F13/32 takes precedence
• CPC Class Codes: G06F 9/3867 using instruction pipelines
• CPC Class Codes: G06F 9/4494 data driven
• CPC Class Codes: H04N 19/13 Adaptive entropy coding, e.g. adaptive variable length coding [AVLC] or context adaptive binary arithmetic coding [CABAC]
• CPC Class Codes: H04N 19/42 characterised by implementation details or hardware specially adapted for video compression or decompression, e.g. dedicated software implementation H04N19/635 takes precedence
• CPC Class Codes: H04N 19/423 characterised by memory arrangements H04N19/433 takes precedence
• CPC Class Codes: H04N 19/61 in combination with predictive coding
• CPC Class Codes: H04N 19/91 Entropy coding, e.g. variable length coding [VLC] or arithmetic coding

Abstract

A multi-standard video decompression apparatus has a plurality of stages interconnected by a two-wire interface arranged as a pipeline processing machine. Control tokens and DATA Tokens pass over the single two-wire interface for carrying both control and data in token format. A token decode circuit is positioned in certain of the stages for recognizing certain of the tokens as control tokens pertinent to that stage and for passing unrecognized control tokens along the pipeline. Reconfiguration processing circuits are positioned in selected stages and are responsive to a recognized control token for reconfiguring such stage to handle an identified DATA Token. A wide variety of unique supporting subsystem circuitry and processing techniques are disclosed for implementing the system.

Claims

1. In a pipeline system having an inverse modeller stage and an inverse discrete cosine transform stage, the improvement comprising:

a processing stage, positioned between said inverse modeller stage and said inverse discrete cosine transform stage, responsive to tokens for processing data, wherein said tokens each comprise a plurality of data words, each said word including an extension indicator which indicates a presence or an absence of additional words in said token, a length of said token being determined by said extension indicators, whereby the length of said token can be unlimited;

wherein said tokens are communicated from said inverse modeller stage to said processing stage.

2. A system as recited in claim 1, wherein said token is a QUANT_-- TABLE token for causing said processing stage to generate a quantization table.

3. A system as recited in claim 1, wherein said token is a QUANT_-- SCALE token.

4. A system as recited in claim 1, wherein said token is a PREDICTION_-- MODE token.

5. A system as recited in claim 1, wherein said token is a SEQUENCE_-- START token.

6. A system as recited in claim 1, wherein said token is a CODING_-- STANDARD token.

7. A system as recited in claim 1, wherein said token is a JPEG_-- TABLE_-- SELECT token.

8. A system as recited in claim 1, wherein said token is a MPEG_-- TABLE_-- SELECT token.

9. A system as recited in claim 1, wherein said extension indicator is an extension bit.

10. A system as recited in claim 1, wherein said processing stage is connected to said inverse modeller stage and said inverse discrete cosine transform stage by a two-wire link defining a sender, and a receiver, and said system further comprises a clock connected to said sender and said receiver, wherein data is transferred from said sender to said receiver upon a transition of said clock only when said sender is ready and said receiver is ready.

11. A system as recited in claim 10, wherein said two wire link further comprises:

electrical validation circuitry in at least one of said sender and said receiver to generate a validation signal for a first state when data stored in said stage is valid and for a second state when data stored in said stage is invalid, said validation circuitry including at least one storage device to store said validation signal;

an acceptance signal connected between said sender and said receiver conveying an acceptance signal indicative of the ability of said receiver to load data stored in the sender; and

enabling circuitry connected to said storage devices for generating an enabling signal to enable loading of data and validation signals into said storage device;

wherein;

said storage device includes a primary data storage device and a secondary data storage device;

said data is loaded into said respective primary data storage devices and said validation signal is loaded into a respective secondary validation storage device at the same time;

data is loaded into said respective primary data storage device when said acceptance signal assumes an enabling state; and

said acceptance signal assumes said enabling state only when the acceptance signal associated with the data storage device of said receiver is in said enabling state or said data in said data storage device of said receiver is invalid.