Method of monitoring system bus traffic by a CPU operating with reduced power

• US 5,809,314 A
• Filed: 04/02/1997
• Issued: 09/15/1998
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Crawford, John, Carmean, Douglas M.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): PHAN, RAYMOND NGAN
• Application Number:
  US08/832,045
• Time in Patent Office: 531 Days
• Field of Search: 395/750.03, 395/750.05, 395/750.07, 395/750.08, 711/135, 711/141, 711/142, 711/143, 711/146
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3215 Monitoring of peripheral devices
• CPC Class Codes: G06F 1/3275 Power saving in memory, e.g. RAM, cache
• CPC Class Codes: G06F 12/0831 using a bus scheme, e.g. with bus monitoring or watching means
• CPC Class Codes: G06F 2212/1028 Power efficiency
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

The present invention provides a method for maintaining cache coherency while minimizing the power consumption. The method includes operating a first processor in a reduced power mode. While the first processor is operating in a reduced power mode, certain portions of the internal logic in the first processor remain clocked so that the first processor continues to monitor transactions on the system bus. The second processor runs a transaction on the system bus to request data. In the event that the first processor determines that the transaction by the second processor is requesting cache data that is stored in the first processor in a modified state, the first processor signals the second processor. After the current bus cycle is completed, the first processor writes back the modified cache line on the system bus and second processor re-runs the transaction on the system bus.

Claims

1. In a multiprocessor computer system, a method for maintaining data coherency in a reduced power operating mode, comprising the steps of:

placing a first processor in a reduced power mode;

monitoring activity on a common bus using circuitry of the first processor that is active in the reduced power mode;

detecting a transaction initiated by a second processor that requires data cached by the first processor, wherein the data is present in other locations than a cache of the first processor, and wherein a version of the data cached by the first processor is a most recent version;

completing the transaction initiated by the second processor;

writing back the most recent version; and

reexecuting the transaction initiated by the second processor using the most recent version.

2. The method of claim 1, further comprising the steps of, while in the reduced power mode, maintaining certain circuitry in an active state, including:

bus unit circuitry;

internal interrupt circuitry; and

snoop logic circuitry.

3. The method of claim 2, wherein the step of detecting includes snooping the common bus while in the low power mode.

4. The method of claim 3, further comprising the step of initiating a request for the common bus so that the first processor can perform a write back of the most recent version.

5. The method of claim 4 wherein the step of writing back the most recent version comprises the first processor mastering the common bus.