Method for reducing the number of coherency cycles within a directory-based cache coherency memory system uitilizing a memory state cache

• US 5,809,536 A
• Filed: 12/09/1996
• Issued: 09/15/1998
• Est. Priority Date: 12/09/1996
• Status: Expired due to Term

• Current Assignee: NCR Corporation
• Original Assignee: Intel Corporation
• Inventors: James, Larry C., Stevens, Roy M., Young, Gene F.
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): PEIKARI, BEHZAD
• Application Number:
  US08/763,703
• Time in Patent Office: 645 Days
• Field of Search: 711/119, 711/120, 711/126, 711/130, 711/141, 711/144, 711/145, 711/148, 711/152, 711/156, 711/163
• US Class Current: 711/144
• CPC Class Codes: G06F 12/082 Associative directories G06F12/0822 takes precedence

Abstract

An improved method for performing state cache line replacement operations in a multiprocessor computer system including plurality if data cache memories, a shared system memory, a state cache memory, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within the shared system memory and the plurality of data cache memories. The method for performing state cache line replacement operations includes the steps of: establishing a default system memory line state of SHARED for lines of memory represented in said state cache memory; reading the system memory line state for a previously stored state cache entry prior to a replacement of said previously stored state cache entry, said previously stored state cache entry being associated with a line of memory stored in said shared memory and at least one data cache memory; and performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED. Since most lines of memory are in a shared state prior to replacement, setting the default state to a shared state, rather than a uncached state, reduces the number of invalidate coherency operations which must be performed during state cache line replacements.

Claims

1. In a multiprocessor computer system including a shared system memory, a state cache memory, a plurality of data cache memories, a system of busses interconnecting said system memory with said plurality of data cache memories, and employing a centralized/distributed directory-based cache coherency system for maintaining consistency between lines of memory within said shared system memory and said plurality of data cache memories;

a method for replacing entries within said state cache memory, said method comprising the steps of;

establishing a default system memory line state of SHARED for lines of memory represented in said state cache memory;

reading the system memory line state for a previously stored state cache entry prior to a replacement of said previously stored state cache entry, said previously stored state cache entry being associated with a line of memory stored in said shared memory and at least one data cache memory;

performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED.

2. In a centralized/distributed directory-based cache coherency system within a computer system including multiple processors;

a data cache memory associated with each processor, each one of said data cache memories containing a data cache memory line state with each line of memory saved within said data cache memories, said data cache memory line state being any one of the group;

MODIFIED, EXCLUSIVE, SHARED, or INVALID;

a system memory shared by said multiple processors, a state cache memory, said state cache memory containing a system memory line state for a predetermined number of lines of memory saved within said system memory, said system memory line state being any one of the group;

SHARED BUS A, SHARED BUS B, SHARED BOTH, OWNED BUS A and OWNED BUS B; and

first (BUS A) and second (BUS B) memory busses, each memory bus connecting a subset of said multiple processors and associated data cache memories;

said system memory and said state cache memory;

a method for replacing entries within said state cache memory, said method comprising the steps of;

reading the system memory line state for a previously stored state cache entry prior to a replacement of said previously stored state cache entry, said previously stored state cache entry being associated with a line of memory stored in said shared memory and at least one data cache memory;

performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED BUS A; and

performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED BUS B.

3. In a centralized/distributed directory-based cache coherency system within a computer system including multiple processors;

a data cache memory associated with each processor, each one of said data cache memories containing a data cache memory line state with each line of memory saved within said data cache memories, said data cache memory line state being any one of the group;

MODIFIED, EXCLUSIVE, SHARED, or INVALID;

a system memory shared by said multiple processors, a state cache memory, said state cache memory containing a system memory line state for a predetermined number of lines of memory saved within said system memory, said system memory line state being any one of the group;

SHARED BUS A, SHARED BUS B, SHARED BOTH, OWNED BUS A and OWNED BUS B; and

first (BUS A) and second (BUS B) memory busses, each memory bus connecting a subset of said multiple processors and associated data cache memories;

said system memory and said state cache memory;

a method for replacing entries within said state cache memory, said method comprising the steps of;

establishing a default system memory line state of SHARED BUS A for lines of memory represented in said state cache memory;

reading the system memory line state for a previously stored state cache entry prior to a replacement of said previously stored state cache entry, said previously stored state cache entry being associated with a line of memory stored in said shared memory and at least one data cache memory;

performing an invalidate operation to assign a data cache memory line state of INVALID to said line of memory in each data cache memory connected to said second memory bus (BUS B) containing said line of memory if said system memory line state for said previously stored state cache entry is SHARED BOTH;

performing an invalidate operation to assign a data cache memory line state of INVALID to said line of memory in each data cache memory connected to said second memory bus (BUS B) containing said line of memory if said system memory line state for said previously stored state cache entry is SHARED BOTH;

performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED BUS A; and

performing a castout operation to update the line of memory within said shared memory and assigning a data cache memory line state of SHARED to said line of memory in each data cache memory containing said line of memory if said system memory line state for said previously stored state cache entry is OWNED BUS B.