DRAM arbiter for video decoder

• US 5,809,538 A
• Filed: 02/07/1996
• Issued: 09/15/1998
• Est. Priority Date: 02/07/1996
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: General Instrument Corporation (CommScope Holding Company, Inc.)
• Inventors: Pollmann, Stephen C., Yilmaz, Serdar
• Primary Examiner(s): Swann, Tod R.
• Assistant Examiner(s): TZENG, FRED
• Application Number:
  US08/598,199
• Time in Patent Office: 951 Days
• Field of Search: 395/433, 395/233, 395/517, 395/520, 395/293, 395/877, 395/728, 395/305, 395/222, 395/861, 395/182.04, 395/294, 395/800, 395/478, 395/729, 348/718
• US Class Current: 711/151
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A memory control and management system efficiently multiplexes access to a dynamic random access memory (DRAM) among several client processes in an MPEG or similar digital television delivery system or the like. These processes can include, for example, an on-screen display (OSD) graphics processor, a microprocessor interface, graphics accelerator functions, and audio and data processors. An arbiter receives packetized data from an MPEG transport layer for distribution to an associated DRAM. The arbiter sequentially time-multiplexes access to the DRAM by the client processes according to priority criteria, including the bandwidth requirements of the client processes, and whether a client process is requesting access. Access is granted for a predetermined period as long as the client is requesting access. Access can be terminated early if the client no longer requests access, or if a new row in the DRAM must be addressed, and the re-addressing period will consume the remainder of the available data transfer cycles in the access period. The invention is particularly applicable to a digital video decoder where an on-screen display graphics processor consumes a large portion of the DRAM interface bandwidth.

Claims

1. Apparatus for controlling access to a memory via a memory interface by a plurality of client processes, comprising:

an arbiter for providing access opportunities to said memory by said client processes in a predetermined client process sequence for data transfer between the memory and the client processes; and

a controller for addressing said memory according to the client process which is currently provided access;

wherein;

the client processes are granted access opportunities to said memory for a predetermined number of access periods; and

access to the memory is granted to a current client process that requests access for up to the predetermined number of access periods, but access to the memory is terminated before the predetermined number of access periods have elapsed if the current client process no longer requires access to said memory, and is granted instead to the client process requesting access which follows the current client process in the client process sequence for at least a portion of a remainder of the predetermined number of access periods.

2. The apparatus of claim 1, wherein:

said memory is a DRAM with addresses comprising rows and columns, and the provision of access to a selected client process is terminated before said predetermined number of access periods have elapsed when said selected client process requires addressing a different row of said memory.

3. The apparatus of claim 2, wherein:

said access is terminated before the predetermined number of access periods have elapsed only when said addressing of a different row would consume a remainder of access periods allocated to the selected client process.

4. The apparatus of claim 1 wherein said client processes include on-screen display graphics for output to a display device.

5. The apparatus of claim 4 wherein said arbiter allocates a majority of its bandwidth to said on-screen display graphics client process.

6. The apparatus of claim 1 wherein said arbiter includes a packet processor for receiving and demultiplexing packet data and storing said demultiplexed data in said DRAM for use by other ones of said client processes.

7. The apparatus of claim 1, wherein:

the client processes are granted access opportunities to said memory for a predetermined number of access periods according to a predetermined bandwidth which is assigned to each of said client processes.

8. The apparatus of claim 1, wherein:

access to the memory is not granted to the client processes that are not requesting access.

9. A memory arbiter for selectively providing access to a memory by a plurality of client processors in a digital television system, wherein:

said client processors include a packet processor, microprocessor interface, and an on-screen display (OSD) graphics processor;

said arbiter provides said access in accordance with predetermined bandwidths which are assigned to each of said client processors by servicing said client processors in a client processor sequence and at a relative frequency determined by said predetermined bandwidths;

the client processors are granted access opportunities to said memory for a predetermined number of access periods according to the assigned predetermined bandwidths; and

access to the memory is granted to a current client processor that requests access for up to the predetermined number of access periods, but access to the memory is terminated before the predetermined number of access periods have elapsed if the current client processor no longer requires access to said memory, and is granted instead to the client processor requesting access which follows the current client process in the client process sequence for at least a portion of a remainder of the predetermined number of access periods.

10. The memory arbiter of claim 9 wherein said memory is a dynamic random access memory (DRAM) with addresses comprising rows and columns, further comprising:

means for terminating access by a selected one of said client processors before the predetermined number of access periods have elapsed when said selected client processor requires addressing of a different row in said memory.

11. The memory arbiter of claim 10, wherein:

access to the memory is terminated before the predetermined number of access periods have elapsed only when said addressing of a different row would consume a remainder of access periods allocated to the current client processor.

12. The memory arbiter of claim 9, wherein:

the client processes are granted access opportunities to said memory for a predetermined number of access periods according to a predetermined bandwidth which is assigned to each of said client processes.

13. The memory arbiter of claim 9, wherein:

access to the memory is not granted to the client processes that are not requesting access.

14. A method for controlling access to a memory via a memory interface by a plurality of client processes, comprising the steps of:

defining access opportunities for each of said client processes to access said memory over a predetermined number of access periods; and

granting access to the memory to a current client process that requests access for up to the predetermined number of access periods, but terminating access to the memory before the predetermined number of access periods have elapsed if the current client process no longer requires access to said memory, and instead granting access to the client process requesting access which follows the current client process in the client process sequence for at least a portion of a remainder of the predetermined number of access periods.

15. The method of claim 14 wherein said memory is a DRAM with addresses comprising rows and columns, comprising the further step of:

terminating access by a selected client process before said predetermined number of access periods have elapsed when said selected client process requires addressing of a different row in said memory.

16. The method of claim 15 wherein said access is terminated early only when said addressing of a different row would consume the remainder of access periods allocated to the selected client process.

17. The method of claim 14 comprising the further steps of:

providing packet data to a packet processor associated with said arbiter;

demultiplexing said packet data; and

storing said demultiplexed packet data in said memory for subsequent transfer to said client processes.

18. The method of claim 14, wherein:

access opportunities to said memory are defined for a predetermined number of access periods according to a predetermined bandwidth which is assigned to each of said client processes.

19. The method of claim 14, wherein:

access to the memory is not granted to the client processes that are not requesting access.