Nitrogenated trench liner for improved shallow trench isolation

• US 5,811,347 A
• Filed: 04/29/1996
• Issued: 09/22/1998
• Est. Priority Date: 04/29/1996
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chang, Kuang-Yeh, Gardner, Mark I., Hause, Fred N.
• Primary Examiner(s): DANG, TRUNG Q
• Application Number:
  US08/641,028
• Time in Patent Office: 876 Days
• Field of Search: 438/424, 438/435, 438/296, 438/221, 438/788, 148/DIG. 50
• US Class Current: 438/435
• CPC Class Codes: H01L 21/0217 the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz H01L21/02126 and H01L21/0214 take precedence
• CPC Class Codes: H01L 21/022 the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides adhesion layers or buffer layers H01L21/02304, H01L21/02362
• CPC Class Codes: H01L 21/3144 on silicon
• CPC Class Codes: H01L 21/3185 of siliconnitrides
• CPC Class Codes: H01L 21/76224 using trench refilling with dielectric materials trench filling with polycristalline silicon H01L21/763; together with vertical isolation, e.g. trench refilling in a SOI substrate H01L21/76264
• CPC Class Codes: Y10S 148/05 Etch and refill

Abstract

A method of forming an improved isolation trench between active regions within the semiconductor substrate. The improved method incorporates a trench liner having a nitrogen content of approximately 0.5 to 2.0 percent. A pad layer is formed on a silicon substrate and a nitride layer is formed on the pad layer. Thereafter, a photoresist layer is patterned on the silicon nitride layer such that regions of the nitride layer are exposed where an isolation trench will subsequently be formed. Next, the exposed regions of the nitride layer and the pad layer situated below the exposed regions of the nitride layer are etched away to expose regions of the silicon substrate. Subsequently, isolation trenches are etched into the silicon substrate with a dry etch process. A trench liner is then formed and nitrogen incorporated into the trench liner. Incorporation of nitrogen into the trench liner can be accomplished by either forming the trench liner in the presence of a nitrogen bearing ambient or by forming a pure SiO₂ trench liner and subsequently implanting the SiO₂ trench liner with nitrogen. After formation of the nitrogenated trench liner, the trench is filled with a dielectric preferably comprised of a CVD oxide. Thereafter, the CVD fill dielectric is planarized and the nitride layer is stripped away.

Claims

1. A method for forming an improved isolation trench comprising:

forming a pad layer on a silicon substrate;

depositing a silicon nitride layer on said pad layer;

patterning a photoresist layer on said silicon nitride layer such that regions of said nitride layer are exposed;

removing said exposed regions of said nitride layer and said pad layer situated below said exposed regions of said nitride layer to expose regions of said silicon substrate;

etching trenches into said exposed regions of said silicon substrate, wherein said trenches comprise sidewalls and a trench floor;

implanting nitrogen into said sidewalls and said trench floor;

filling said trench with a dielectric;

planarizing said dielectric such that an upper surface of said dielectric is substantially coplanar with an upper surface of said nitride layer; and

removing said nitride layer.

2. The method of claim 1, further comprising forming an oxide on said sidewalls and said floor.

3. The method of claim 2 wherein said oxide is deposited by chemical-vapor deposition.

4. The method of claim 2 wherein said oxide is thermally grown.

5. The method of claim 2 wherein said oxide is 50 to 700 angstroms thick.

6. The method of claim 1 wherein said implanting comprises a first nitrogen implant performed at 0°

, a second implant performed at 45°

, and a third implant performed at -45°

.

7. The method of claim 2 wherein said nitrogen is implanted through said oxide formed on said sidewalls and said floor.

8. The method of claim 1 wherein said dielectric comprises CVD oxide formed from a TEOS source.

9. The method of claim 1 wherein said planarizing said dielectric comprises polishing said dielectric with a chemical mechanical polish.

10. A method for forming an isolation structure between a pair of active regions comprising:

providing a semiconductor substrate having an isolation region interposed between a pair of active regions;

removing an upper region of said semiconductor substrate within said isolation region to form a trench, wherein said trench is bounded by a trench sidewall and a trench floor;

implanting nitrogen into said trench sidewall and said trench floor to form a nitrogenated trench; and

filling said nitrogenated trench with a dielectric to form an isolation structure.

11. The method of claim 10, further comprising forming an oxide layer upon said trench sidewall and said trench floor prior to said implanting nitrogen.

12. The method of claim 10, further comprising forming an oxide layer upon said trench sidewall and said trench floor subsequent to said implanting nitrogen.

13. The method of claim 10, wherein said implanting nitrogen comprises performing a first nitrogen implant at 0°

, a second implant at 45°

, and a third implant at -45°

.