Laser antifuse using gate capacitor

• US 5,811,869 A
• Filed: 01/04/1996
• Issued: 09/22/1998
• Est. Priority Date: 01/04/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Ma, Manny K. F., Seyyedy, Mirmajid
• Primary Examiner(s): CARROLL, JAMES J
• Application Number:
  US08/582,652
• Time in Patent Office: 992 Days
• Field of Search: 257/530, 257/410, 438/600
• US Class Current: 257/530
• CPC Class Codes: G11C 17/16 using electrically-fusible links
• CPC Class Codes: H01L 23/5254 the change of state resulting from the use of an external beam, e.g. laser beam or ion beam
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/0002 Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Abstract

An integrated circuit laser antifuse is described which has two physical states. In the first physical state the laser antifuse has to conductive plates electrically separated by a layer of dielectric material. In the second physical state the two conductive plates are electrically connected through the dielectric in response to an external radiation source, such as a laser.

Claims

1. A laser antifuse, having first and second physical states, fabricated in an integrated circuit, the laser antifuse comprising:

a first conductive plate;

a second conductive plate; and

a layer of BaSrTiO₃ dielectric material located between the first conductive plate and the second conductive plate,

wherein the first conductive plate and the second conductive plate are electrically isolated by the layer of BaSrTiO₃ dielectric material in the first physical state, and wherein the first conductive plate and the second conductive plate are electrically connected through the layer of BaSrTiO₃ dielectric material in the second physical state in response to a focused external radiation source.

2. The laser antifuse of claim 1 wherein the first conductive plate comprises:

a layer of polysilicon fabricated on the layer of dielectric material.

3. The laser antifuse of claim 1 wherein the second conductive plate comprises:

an N-well fabricated in a P-substrate of the integrated circuit.

4. The laser antifuse of claim 3 wherein the second conductive plate further comprises:

an N+ contact region fabricated in the N-well.

5. The laser antifuse of claim 1 wherein the second conductive plate comprises:

a P-well fabricated in an N-substrate of the integrated circuit.

6. The laser antifuse of claim 5 wherein the second conductive plate further comprises:

a P+ contact region fabricated in the P-well.

7. The laser antifuse of claim 1 wherein the focused external radiation source comprises a laser.

8. The laser antifuse of claim 1 wherein the dielectric material is a layer of oxide.

9. The laser antifuse of claim 1 wherein the integrated circuit is a dynamic random access memory (DRAM).

10. A laser antifuse, having first and second physical states, fabricated in an integrated memory circuit, the laser antifuse comprising:

a first conductive plate, the first conductive plate being a layer of polysilicon;

a second conductive plate, the second conductive plate being a well fabricated in a substrate of the integrated memory circuit; and

a layer of BaSrTiO₃ dielectric material located between the first conductive plate and the second conductive plate,

wherein the first conductive plate and the second conductive plate are electrically isolated by the layer of BaSrTiO₃ dielectric material in the first physical state, and wherein the first conductive plate and the second conductive plate are electrically connected through the layer of BaSrTiO₃ dielectric material in the second physical state in response to a focused external radiation source.

11. The laser antifuse of claim 10 wherein the integrated memory circuit is a dynamic random access memory (DRAM).

12. The laser antifuse of claim 10 wherein the second conductive plate comprises:

an N-well fabricated in a P-substrate of the integrated circuit.

13. The laser antifuse of claim 10 wherein the second conductive plate comprises:

a P-well fabricated in an N-substrate of the integrated memory circuit.

14. The laser antifuse of claim 10 wherein the focused external radiation source comprises a laser.

15. A method of programming a laser antifuse, the method comprising the steps of:

fabricating an integrated circuit having a laser antifuse, the laser antifuse comprising,

a first conductive plate,

a second conductive plate, and

a layer of BaSrTiO₃ dielectric material located between the first conductive plate and the second conductive plate, wherein the first conductive plate and the second conductive plate are electrically isolated by the layer of BaSrTiO₃ dielectric; and

electrically connecting the first conductive plate and the second conductive plate by focussing an external radiation source on the first conductive plate such that a conductive path is formed through the layer of BaSrTiO₃ dielectric material.

16. The method of claim 15 wherein the external radiation source is a laser.

17. The method of claim 15 wherein the first conductive plate is polysilicon, and the second conductive plate is a well fabricated in a substrate of the integrated circuit.

18. The method of claim 15 wherein the dielectric material is a layer of oxide fabricated on the second conductive plate.