Test ring oscillator

• US 5,811,983 A
• Filed: 09/03/1996
• Issued: 09/22/1998
• Est. Priority Date: 09/03/1996
• Status: Expired due to Term

• Current Assignee: Ip-First LLC A Delaware Limited Liability Company
• Original Assignee: Integrated Device Technology Incorporated (Renesas Electronics Corporation)
• Inventors: Lundberg, James R.
• Primary Examiner(s): BROWN, GLENN WARNER
• Assistant Examiner(s): Phung, Anh
• Application Number:
  US08/707,151
• Time in Patent Office: 749 Days
• Field of Search: 324/763, 324/764, 324/765, 368/100-125, 371/22.5-22.6
• US Class Current: 324/750.3
• CPC Class Codes: G01R 31/2882 Testing timing characteristics
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test

Abstract

An apparatus and method for measuring parasitic differences between dissimilar conductive paths on a semiconductor is provided. The apparatus provides a ring oscillator which has two propagation paths. The first path is traversed on a logical transition from low to high, and the second path is traversed on a logical transition from high to low. The gate stages for the first path may be interconnected via a metal conductive layer, and the gate stages for the second path may be connected to a dissimilar metal, or polycide, for example. A single output signal is produced which has a period equal to twice the delay of the inverter stages, plus any delay associated with the parasitic difference in the two paths. The duty cycle of the periodic signal may then be used to determine the parasitic difference between the two materials used to interconnect the stages in the ring oscillator.

Claims

1. A test apparatus for quantifying parasitics on a microprocessor, the test apparatus comprising:

a plurality of first gate stages, said first gate stages having a first portion and a second portion;

a plurality of second gate stages, said second gate stages having a first portion and a second portion, said second gate stages connected in between said plurality of first gate stages, wherein said plurality of first gate stages and said plurality of second gate stages are connected together to form a ring oscillator, said ring oscillator producing a periodic signal;

a first signal path within said ring oscillator, said first signal path flowing through said first portion of said plurality of first gate stages and said first portion of said plurality of second gate stages;

a second signal path within said ring oscillator, said second signal path flowing through said second portion of said plurality of first gate stages and said second portion of said plurality of second gate stages;

a test node, connected between one of said plurality of first gate stages and one of said plurality of second gate stages, for monitoring said periodic signal produced by said ring oscillator;

wherein the high portion of said periodic signal produced by said ring oscillator at said test node flows through said first signal path, and the low portion of said periodic signal produced by said ring oscillator at said test node flows through said second signal path;

whereby the relationship of said high portion and said low portion of said periodic signal at said test node corresponds to the difference between said parasitics of said first signal path and said second signal path.

2. The test apparatus, as recited in claim 1, wherein said first gate stages comprise a pair of NAND gates.

3. The test apparatus, as recited in claim 2, wherein said first portion comprises a first input into both of said pair of NAND gates.

4. The test apparatus, as recited in claim 3, wherein said second portion comprises a second input into both of said pair of NAND gates.

5. The test apparatus, as recited in claim 1, wherein said second gate stages comprise a pair of NOR gates.

6. The test apparatus, as recited in claim 5, wherein said first portion comprises a first input into both of said pair of NOR gates.

7. The test apparatus, as recited in claim 6, wherein said second portion comprises a second input into both of said pair of NOR gates.

8. The test apparatus, as recited in claim 1, wherein said first gate stages and said second gate stages are alternately connected serially to form said ring oscillator.

9. The test apparatus, as recited in claim 1, wherein there are an odd cumulative number of said first and second gate stages in said ring oscillator.

10. The test apparatus, as recited in claim 1, wherein said periodic signal is a digital signal.

11. The test apparatus, as recited in claim 1, wherein when said interconnection parasitics are the same for said first signal path and said second signal path, said periodic signal has a duty cycle that is approximately 50%.

12. The test apparatus, as recited in claim 1, wherein when said interconnection parasitics are not the same for said first signal path and said second signal path, said periodic signal has a duty cycle that is not 50%.

13. The test apparatus, as recited in claim 12, wherein said duty cycle corresponds to the difference between said interconnection parasitics of said first signal path and said second signal path.

14. The test apparatus, as recited in claim 1, wherein the connection between said first portion of said first and second gate stages is made without metal.

15. The test apparatus, as recited in claim 1, wherein the connections between said first portions of said first and second gate stages are made using polysilicon, or a polysilicon silicide combination (polycide).

16. The test apparatus, as recited in claim 1, wherein the connections between said second portions of said first and said second gate stages are made using metal.

17. The test apparatus, as recited in claim 1, wherein the connections between said first portions and said second portions of said first and second gate stages are made with metals having different interconnection parasitics.

18. The test apparatus, as recited in claim 1 wherein said interconnection parasitics comprise electrical impedance characteristics of said connections between said first and said second gate stages.

19. The test apparatus, as recited in claim 18, wherein said impedance characteristics comprise the capacitance and resistance of said connections.

20. The test apparatus, as recited in claim 1, further comprising:

an enable signal, connected to either a first or second portion of one of said plurality of first gate stages, for enabling said ring oscillator to produce said periodic signal.

21. A semiconductor device, manufactured on a substrate, the semiconductor device having a plurality of transistors connected together with interconnection materials having dissimilar electrical parasitics, the semiconductor device having a plurality of test circuits, the test circuits providing indicia of the electrical parasitics of the interconnection materials, each of the test circuits comprising:

a dual path ring oscillator, said ring oscillator comprising;

a plurality of gate stages connected together to form a ring;

a first path through said gate stages connected using a first interconnection material; and

a second path through said gate stages connected using a second interconnection material;

wherein said first path and said second path through said gate stages produces a periodic signal, said signal having a duty cycle corresponding to the electrical parasitic difference between said first interconnection material and said second interconnection material; and

a test node, connected between two of said plurality of gate stages, for detecting said periodic signal.

22. The semiconductor device, as recited in claim 21, wherein said electrical parasitics of said interconnection materials comprise the resistance and capacitance of said materials.

23. The semiconductor device, as recited in claim 21, wherein said plurality of gate stages further comprises:

an alternating pair of logic gates, each of said alternating pair having a first portion and a second portion, said first portion connected to said first interconnection material, and said second portion connected to said second interconnection material.

24. The semiconductor device, as recited in claim 23, wherein said alternating pair further comprises:

a NAND gate structure; and

a NOR gate structure, connected to said NAND gate structure.

25. The semiconductor device, as recited in claim 24, wherein said NAND gate structure comprises a pair of NAND gates, and said NOR gate structure comprises a pair of NOR gates.

26. The semiconductor device, as recited in claim 24, wherein said first portion comprises a first set of inputs into both of said NAND gate structure and said NOR gate structure;

and said second portion comprises a second set of inputs into both of said NAND gate structure and said NOR gate structure.

27. The semiconductor device, as recited in claim 26, wherein said first set of inputs provides said first path through said gate stages, and said second set of inputs provides said second path through said gate stages.

28. The semiconductor device, as recited in claim 21, wherein said first path provides propagation of said periodic signal through said ring oscillator when said periodic signal at said test node transitions from low to high.

29. The semiconductor device, as recited in claim 21, wherein said second path provides propagation of said periodic signal through said ring oscillator when said periodic signal at said test node transitions from high to low.

30. The semiconductor device, as recited in claim 21, wherein the high portion of said periodic signal at said test node propagates through said ring oscillator along said first path, and the low portion of said periodic signal at said test node propagates through said ring oscillator along said second path.

31. A method for measuring parasitics on a semiconductor device, the semiconductor device having a dual path test circuit which produces a periodic signal, the method comprising the steps of:

connecting a first interconnection material along a first path of the dual path test circuit;

connecting a second interconnection material along a second path of the dual path test circuit;

measuring the high portion of the periodic signal propagated through the first path;

measuring the low portion of the periodic signal propagated through the second path; and

comparing the measured high and low portions of the periodic signal to determine the parasitic difference between the first and second interconnection materials.

32. The method for measuring parasitics, as recited in claim 31, wherein the duty cycle of the periodic signal is approximately 50% when the first and second interconnection materials have approximately the same parasitics.

33. The method for measuring parasitics, as recited in claim 31, wherein the duty cycle of the periodic signal is not 50% when the first and second interconnection materials have different parasitics.

34. The method for measuring parasitics, as recited in claim 31, wherein parasitics comprise the capacitance and resistance of an interconnection material.

35. The method for measuring parasitics, as recited in claim 31, further comprising the step of:

providing a test pad on the semiconductor device, the test pad being connected to the dual path test circuit, the test pad providing a connection point for measuring the periodic signal.

36. The method for measuring parasitics, as recited in claim 31, wherein the dual path test circuit comprises a ring oscillator.

37. The method for measuring parasitics, as recited in claim 36, wherein the ring oscillator comprises a plurality of logic gates connected in series, with the output of the last logic gate connected to the input of the first logic gate, to form a ring.

38. The method for measuring parasitics, as recited in claim 36, wherein the first and second interconnection material connect the plurality of logic gates to each other.

39. The method for measuring parasitics, as recited in claim 31, wherein the period of the periodic signal corresponds to the cumulative propagation time through the first and second path.