Block clock and initialization circuit for a complex high density PLD
First Claim
1. In a programmable logic device having a plurality of programmable logic blocks, a block-level circuit comprising:
- a plurality of product terms;
a plurality of clock signal input lines;
a plurality of block clock lines coupled to a plurality of macrocells in one programmable logic block;
a plurality of block initialization lines coupled to said plurality of macrocells in said one programmable logic block;
a block clock generator connected to a first set of product terms in said plurality of product terms, to clock signal input lines in said plurality of clock signal input lines, and to said plurality of block clock lines wherein said block clock generator receives input signals on said clock signal input lines and from said product terms, and generates at least one block clock signal on one of said plurality of block clock lines; and
a block initialization circuit connected to a second set of product terms in said plurality of product terms, and to said plurality of block initialization lines wherein said block initialization circuit receives an input signal from said second set of product terms and generates an output signal on one of said plurality of block initialization lines.
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Accused Products
Abstract
A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.
143 Citations
50 Claims
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1. In a programmable logic device having a plurality of programmable logic blocks, a block-level circuit comprising:
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a plurality of product terms; a plurality of clock signal input lines; a plurality of block clock lines coupled to a plurality of macrocells in one programmable logic block; a plurality of block initialization lines coupled to said plurality of macrocells in said one programmable logic block; a block clock generator connected to a first set of product terms in said plurality of product terms, to clock signal input lines in said plurality of clock signal input lines, and to said plurality of block clock lines wherein said block clock generator receives input signals on said clock signal input lines and from said product terms, and generates at least one block clock signal on one of said plurality of block clock lines; and a block initialization circuit connected to a second set of product terms in said plurality of product terms, and to said plurality of block initialization lines wherein said block initialization circuit receives an input signal from said second set of product terms and generates an output signal on one of said plurality of block initialization lines.
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2. In a programmable logic device having a plurality of programmable logic blocks, a block-level circuit comprising:
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a plurality of product terms; a plurality of clock signal input lines; a plurality of block clock signal lines coupled to a plurality of macrocells in one programmable logic block in said plurality of programmable logic blocks; a programmable clock and product-term clock generation circuit comprising; a first generator circuit input terminal connected to one of said plurality of clock signal input lines; a second generator circuit input terminal connected to one product term of said plurality of product terms; and a generator circuit output line wherein said generator circuit output line is one of said block clock lines in said plurality of block clock lines. - View Dependent Claims (3, 4, 5, 6, 7, 8, 9, 10)
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11. In a programmable logic device having a plurality of programmable logic blocks, a block-level circuit comprising:
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a plurality of product terms; a plurality of clock signal input lines; a plurality of block clock signal lines coupled to a plurality of macrocells in a programmable logic block; a programmable clock and product-term clock generation circuit comprising; a clock generator having; a clock terminal coupled to one clock signal input line in said plurality of said clock signal input lines; a clock enable terminal coupled to one product term in said plurality of product terms; and a clock generator output terminal; a programmable clock signal selector having; a first selector input terminal coupled to said clock generator output terminal; a second selector input terminal coupled to said one product term in said plurality of product terms; and a selector output line wherein said programmable clock signal selector selectively connects one selector input terminal to selector output line, and disconnects one other selector input terminal from said selector line; and a programmable polarity control element having both a polarity input terminal and an inverse polarity input terminal connected to said selector output line; and
a polarity output terminal connected to one of said block clock lines in said plurality of block clock lineswherein said programmable polarity control element programmably couples one of said polarity input terminal and said inverse polarity input terminal to said polarity output terminal and decouples the other of said polarity input terminal and said inverse polarity input terminal from said polarity output terminal. - View Dependent Claims (12, 13, 14)
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15. A method of generating a block clock signal comprising:
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coupling a clock signal source having first and second edges to an input terminal of a clock generation circuit wherein said clock generation circuit also comprises a first clock enable terminal, a second clock enable terminal, and an output terminal; coupling a first product term to said first clock enable terminal wherein upon said first product term having a first state, a clock pulse is generated on said output terminal in response to each first edge on said input terminal; and
upon said first product term having a second state, no clock pulse is generated on said output terminal in response to each first edge on said input terminal; andcoupling a second product term to said second clock enable terminal wherein upon said second product term having a first state, a clock pulse is generated on said output terminal in response to each second edge on said input terminal; and
upon said second product term having a second state, no clock pulse is generated on said output terminal in response to each second edge on said input terminal. - View Dependent Claims (16, 17, 18, 19, 20, 21, 22)
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23. In a programmable logic device, a block-level circuit comprising:
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a product term; a clock signal input line; a plurality of block clock lines coupled to a plurality of macrocells in one programmable logic block in a plurality of programmable logic blocks; a programmable dual output clock generation circuit comprising; a first generation circuit input terminal connected to said clock signal input line; a second generation circuit input terminal coupled to said product term; a first generation circuit output terminal connected to a first block clock line in said plurality of block clock signal lines, and coupled to a second block clock signal line in said plurality of block clock signal lines. - View Dependent Claims (24, 25, 26, 27, 28, 29, 30, 31, 32, 33, 34, 35, 36)
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37. A block-level circuit comprising:
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a plurality of product term input lines; a plurality of clock signal input lines; a plurality of block clock lines coupled to a plurality of macrocells in one programmable logic block of a plurality of programmable logic blocks; a programmable multi-function clock and product term clock generator circuit comprising; a first input terminal connected to a first clock signal input line in said plurality of clock signal input lines; a second input terminal connected to a first product term in said plurality of product term input lines; and an output line wherein said output line is a first block clock line in said plurality of block clock lines; and a dual enable biphase clock generator circuit comprising; a first input terminal connected to a second clock signal input line in said plurality of clock signal input lines; a second input terminal connected to a second product term in said plurality of product term input lines; a third input terminal connected to a third product term in said plurality of product term input lines; and an output line wherein said output line is a second block clock line in said plurality of block clock lines. - View Dependent Claims (38, 39, 40)
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41. A block-level circuit comprising:
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a plurality of product term input lines; a plurality of clock signal input lines; a plurality of block clock lines coupled to a plurality of macrocells in a programmable logic block; a programmable multi-function clock and product-term clock generator circuit comprising; a first input terminal connected to a first clock signal input line in said plurality of clock signal input lines; a second input terminal connected to a first product term in said plurality of product term input lines; and an output line wherein said output line is a first block clock line in said plurality of block clock lines; and a dual output multi-function clock generation circuit comprising; a first input terminal connected to a second clock signal input line in said plurality of clock signal input lines; a second input terminal connected to a second product term in said plurality of product term input lines; a first output line wherein said first output line is a second block clock line in said plurality of block clock lines; and a second output line wherein said second output line is a third block clock line in said plurality of block clock lines. - View Dependent Claims (42)
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43. A block-level circuit comprising:
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a plurality of product term input lines; a plurality of clock signal input lines; a plurality of block clock lines coupled to a plurality of macrocells in a programmable logic block; a dual enable biphase clock generator circuit comprising; a first input terminal connected to a first clock signal input line in said plurality of clock signal input lines; a second input terminal connected to a first product term in said plurality of product term input lines; a third input terminal connected to a second product term in said plurality of product term input lines; and an output line wherein said output line is a first block clock line in said plurality of block clock lines a dual output multi-function clock generation circuit comprising; a first input terminal connected to a second clock signal input line in said plurality of clock signal input lines; a second input terminal connected to a third product term in said plurality of product term input lines; a first output line wherein said first output line is a second block clock line in said plurality of block clock lines; and a second output line wherein said second output line is a third block clock line in said plurality of block clock lines. - View Dependent Claims (44)
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45. A method for block clock signal generation comprising:
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coupling a plurality of clock lines to a block-level circuit; coupling a plurality of product terms to said block-level circuit; programmably configuring said block-level circuit to generate a plurality of block clock signals in response to signals on said plurality of clock lines and said plurality of product terms wherein said plurality of block clock signals can include any of a product-term clock signal;
a clock enabled clock signal;
a sum-term clock signal; and
a biphase clock signal. - View Dependent Claims (46)
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47. A method for block clock signal generation comprising:
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coupling a plurality of clock lines to a block-level circuit; coupling a plurality of product terms to said block-level circuit; programmably configuring said block-level circuit to generate a plurality of block clock signals in response to signals on said plurality of clock lines and said plurality of product terms wherein said plurality of block clock signals can include any one of a product-term clock signal; and
a clock enabled clock signal.
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48. A method for block clock signal generation comprising:
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coupling a plurality of clock lines to a block-level circuit; coupling a plurality of product terms to said block-level circuit; generating from said block-level circuit a plurality of block-level clock signals in response to at least one signal on said plurality of clock lines and said plurality of product terms wherein said plurality of block-level clock signals can include any one of a product-term clock signal;
a clock enabled clock signal; and
a biphase clock signal.
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49. A method for block clock signal generation comprising:
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coupling a plurality of clock lines to a block-level circuit; coupling a plurality of product terms to said block-level circuit; generating from said block-level circuit a plurality of block-level clock signals in response to at least one signal on said plurality of clock lines and said plurality of product terms wherein said plurality of block-level clock signals can include any one of a sum-term clock signal;
a clock enabled clock signal; and
a biphase clock signal.
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50. In a programmable logic device, a block-level circuit comprising:
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a plurality of product terms; a plurality of block initialization lines coupled to a plurality of macrocells in one programmable logic block in a plurality of programmable logic blocks; a programmable initialization circuit comprising; a plurality of input terminals coupled to said plurality of product terms; a first output terminal coupled to a first input terminal in said plurality of input terminals to receive the product term coupled to said first input terminal, and connected to a first block initialization line in said plurality of block initialization lines; and a second output terminal coupled to a second input terminal in said plurality of input terminals to receive one of the product term and the inverse of the product term coupled to the second input terminal, and connected to a second block initialization line in said plurality of block initialization lines.
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Specification