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Block clock and initialization circuit for a complex high density PLD

  • US 5,811,987 A
  • Filed: 11/05/1996
  • Issued: 09/22/1998
  • Est. Priority Date: 06/02/1995
  • Status: Expired due to Term
First Claim
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1. In a programmable logic device having a plurality of programmable logic blocks, a block-level circuit comprising:

  • a plurality of product terms;

    a plurality of clock signal input lines;

    a plurality of block clock lines coupled to a plurality of macrocells in one programmable logic block;

    a plurality of block initialization lines coupled to said plurality of macrocells in said one programmable logic block;

    a block clock generator connected to a first set of product terms in said plurality of product terms, to clock signal input lines in said plurality of clock signal input lines, and to said plurality of block clock lines wherein said block clock generator receives input signals on said clock signal input lines and from said product terms, and generates at least one block clock signal on one of said plurality of block clock lines; and

    a block initialization circuit connected to a second set of product terms in said plurality of product terms, and to said plurality of block initialization lines wherein said block initialization circuit receives an input signal from said second set of product terms and generates an output signal on one of said plurality of block initialization lines.

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