Power converter having switching frequency phase locked to system clock

• US 5,811,999 A
• Filed: 12/11/1996
• Issued: 09/22/1998
• Est. Priority Date: 12/11/1996
• Status: Expired due to Fees

• Current Assignee: Fairchild Semiconductor Corporation (ON Semiconductor Corporation)
• Original Assignee: Micro Linear Corporation (Qorvo, Inc.)
• Inventors: Smith, Richard Allen, Hall, George Arthur
• Primary Examiner(s): RUBIN, MARGARET R
• Application Number:
  US08/764,593
• Time in Patent Office: 650 Days
• Field of Search: 327/156, 327/158, 327/243, 327/244
• US Class Current: 327/156
• CPC Class Codes: H02M 3/33507 with automatic control of the output voltage or current, e.g. flyback converters H02M3/33561, H02M3/33569 take precedence
• CPC Class Codes: H04B 15/04 the interference being caused by substantially sinusoidal oscillations, e.g. in a receiver or in a tape-recorder

Abstract

A circuit for synchronizing a periodic ramp signal utilized in a switching mode power converter to system clock signal. A capacitor is charged through a resistor. When a voltage across the capacitor reaches a predetermined level, the capacitor is discharged and the charging cycle is repeated, thereby generating the periodic ramp signal across the capacitor. A waveform shaping circuit shapes the ramp signal into a rectangular wave signal having a same frequency and phase as the ramp signal. A phase comparator compares a phase of the rectangular wave signal to a phase of the system clock signal for forming a phase error signal. The phase error signal controls a level of current supplied to the timing capacitor by a voltage controlled current source. When the frequency of the system clock signal is higher than the frequency of the ramp signal, the phase comparator causes the voltage controlled current source to supply additional current to the capacitor, increasing the frequency of the ramp signal. When the frequency of the system clock signal is lower than the frequency of the ramp signal, the phase comparator causes the voltage controlled current to supply less current to the capacitor, decreasing the frequency of the ramp signal. Therefore, the frequency of the ramp signal is controlled in phase locked loop to synchronize the ramp signal with the system clock signal. The synchronized ramp signal can then be utilized for controlling switching in the switching mode power converter, reducing the effects of switching noise.

Claims

1. An apparatus for synchronizing a periodic ramp signal with a periodic clock signal comprising:

a. a voltage controlled oscillator for forming the periodic ramp signal; and

b. a waveform shaping circuit for forming a periodic rectangular signal having a same frequency as the periodic ramp signal; and

c. a phase comparator for comparing a phase of the periodic rectangular signal to a phase of the periodic clock signal and for controlling the voltage controlled oscillator.

2. The apparatus according to claim 1 wherein a rising edge of the rectangular signal coincides with a falling edge of the periodic ramp signal.

3. The apparatus according to claim 1 wherein a falling edge of the periodic ramp signal is locked to a rising edge of the periodic clock signal.

4. The apparatus according to claim 1 further comprising a power converter wherein the periodic ramp signal is compared to an error signal representative of a difference between a regulated output and a desired output for controlling a duty cycle of a power switch.

5. The apparatus according to claim 1 wherein the waveform shaping circuit comprises:

a. a first transistor having a base, a collector and an emitter wherein the base of the first transistor is coupled to receive the periodic ramp signal and the collector of the first transistor is coupled to a supply node;

b. a first resistor having a first terminal and a second terminal wherein the first terminal of the first resistor is coupled to the emitter of the first transistor and the second terminal of the first resistor is coupled to a ground node;

c. a first capacitor having a first terminal and a second terminal wherein the first terminal of the first capacitor is coupled to the emitter of the first transistor;

d. a diode having an anode and a cathode wherein an anode of the diode is coupled to the second terminal of the first capacitor and the cathode is coupled to the supply node;

e. a second transistor having a base, a collector and an emitter wherein a base of the second transistor is coupled to the anode of the diode;

f. a second resistor having a first terminal and a second terminal wherein the first terminal of the second resistor is coupled to the collector of the second transistor and the second terminal of the second resistor is coupled to the supply node;

g. a second capacitor having a first terminal and a second terminal wherein the first terminal of the second capacitor is coupled to the collector of the second transistor and the second terminal of the second capacitor is coupled to the supply node; and

h. a third resistor having a first terminal and a second terminal wherein the first terminal of the third resistor is coupled to the emitter of the second transistor and the second terminal of the third resistor is coupled to the ground node wherein the rectangular signal is formed at the first terminal of the third resistor.

6. The apparatus according to claim 1 wherein the voltage controlled oscillator comprises:

a. a timing capacitor coupled to receive a first current from a supply node; and

b. a voltage controlled current source coupled to supply a second current to the timing capacitor; and

c. a circuit for discharging the capacitor when a voltage across the capacitor reaches a predetermined level.

7. The apparatus according to claim 6 wherein the voltage controlled current source comprises a transistor.

8. An apparatus for synchronizing a periodic ramp signal with a periodic clock signal comprising:

a. a phase comparator having a first input, a second input and an output, wherein the first input is coupled to receive the periodic clock signal and the second input is coupled to receive a signal representative of the periodic ramp signal;

b. a current source coupled to be controlled by the output of the phase comparator; and

c. a timing capacitor coupled to be charged by a current supplied by the current source wherein the periodic ramp signal is formed across the capacitor and a frequency of the ramp signal is dependent upon a level of current supplied by the voltage controlled current source.

9. The apparatus according to claim 8 wherein a falling edge of the periodic ramp signal is locked to a rising edge of the periodic clock signal.

10. The apparatus according to claim 8 wherein the capacitor is discharged when a voltage across the capacitor reaches a predetermined level.

11. The apparatus according to claim 8 wherein the current source draws current from the timing capacitor when the output of the phase comparator is in a first condition and supplies current to the timing capacitor when the output of the phase comparator is in a second condition.

12. The apparatus according to claim 11 wherein the first condition occurs when a frequency of the periodic clock signal is lower than the frequency of the ramp signal and wherein the second condition occurs when the frequency of the periodic clock signal is higher than the frequency of the ramp signal.

13. The apparatus according to claim 11 wherein the current source is a push-pull transistor pair.

14. The apparatus according to claim 8 wherein the current source is a transistor.

15. The apparatus according to claim 8 further comprising a low pass filter coupled between the phase comparator and the current source.

16. The apparatus according to claim 8 wherein the timing capacitor is also charged through a resistor by a supply voltage.

17. The apparatus according to claim 8 wherein the signal representative of the periodic ramp signal is a periodic rectangular signal wherein a falling edge of the rectangular signal coincides with a rising edge of the rectangular signal.

18. The apparatus according to claim 8 further comprising a power converter wherein the periodic ramp signal is compared to an error signal representative of a difference between a regulated output and a desired output for controlling a duty cycle of a power switch.

19. A method of synchronizing a periodic ramp signal with a periodic clock signal comprising the step of:

a. forming a current signal wherein a level of the current signal is representative of a difference in phase between the periodic ramp signal and the periodic clock signal; and

b. charging a charge storage device with the current signal and periodically discharging the charge storage device thereby forming the periodic ramp signal across the charge storage device.

20. The method according to claim 19 further comprising the step of discharging the charge storage device each time a voltage across the charge storage device reaches a predetermined level.

21. The method according to claim 20 further comprising steps of:

a. comparing the periodic ramp signal is to an error signal representative of a difference between a regulated output and a desired output;

b. controlling a duty cycle of a power switch based upon a result of the step of comparing.

22. The method according to claim 21 further comprising a step of forming a signal representative of the periodic ramp signal wherein a falling edge of the signal representative of the periodic ramp signal coincides with a rising edge of the rectangular signal.

23. The method according to claim 21 wherein a falling edge of the periodic ramp signal is coincides with a rising edge of the periodic clock signal.

24. The method according to claim 21 wherein the current signal is formed by a transistor coupled to the charge storage device.

25. The method according to claim 24 wherein the current signal is also formed by a resistor coupled to the charge storage device.