Method for performing simulation using a hardware logic emulation system

• US 5,812,414 A
• Filed: 12/19/1996
• Issued: 09/22/1998
• Est. Priority Date: 10/05/1988
• Status: Expired due to Term

• Current Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Original Assignee: Quickturn Design Systems Incorporated (Cadence Group)
• Inventors: Butts, Michael R., Batcheller, Jon A.
• Primary Examiner(s): Trans, Vincent N.
• Application Number:
  US08/770,655
• Time in Patent Office: 642 Days
• Field of Search: 364/488, 364/489, 364/490, 364/578, 395/500
• US Class Current: 716/103
• CPC Class Codes: G06F 30/331 with hardware acceleration, e.g. by using field programmable gate array [FPGA] or emulation
• CPC Class Codes: G06F 30/34 for reconfigurable circuits, e.g. field programmable gate arrays [FPGA] or programmable logic devices [PLD]
• CPC Class Codes: G06F 30/347 Physical level, e.g. placement or routing
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347

Abstract

A plurality of electronically reconfigurable gate array (ERCGA) logic chips are interconnected via a reconfigurable interconnect, and electronic representations of large digital networks are converted to take temporary actual operating hardware form on the interconnected chips. The reconfigurable interconnect permits the digital network realized on the interconnected chips to be changed at will, making the system well suited for a variety of purposes including simulation, prototyping, execution and computing. The reconfigurable interconnect may comprise a partial crossbar that is formed of ERCGA chips dedicated to interconnection functions, wherein each such interconnect ERCGA is connected to at least one, but not all of the pins of a plurality of the logic chips. Other reconfigurable interconnect topologies are also detailed.

Claims

1. A method for stimulating a functional circuit with logical stimulus to determine what response is produced by the functional circuit from that input, the method comprising the steps:

(a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reprogrammable logic devices, where N is a number greater than one, said N reprogrammable logic devices interconnected by reprogrammable interconnect devices, said functional circuit being implemented by at least two of said N reprogrammable logic devices;

(b) converting the logical stimulus into input electrical signals;

(c) inputting said electrical signals to said N reconfigurable logic apparatus which is configured with the functional circuit;

(d) receiving output electrical signals from said reconfigurable logic apparatus; and

(e) converting said output electrical signals into software form.

2. The method of claim 1 wherein each step is performed in seriatim from step (a) to step (e).

3. The method of claim 1 wherein each of said N reprogrammable logic devices comprises a field programmable gate array.

4. The method of claim 1 wherein said software form is translatable by a computer into a user-readable format.

5. A method of simulating a functional circuit design, the method comprising the steps of:

(a) configuring a reconfigurable logic apparatus to implement the functional circuit, said reconfigurable logic apparatus comprising N reprogrammable logic devices, where N is a number greater than one, said N reprogrammable logic devices interconnected by reprogrammable interconnect devices, said functional circuit being implemented by at least two of said N reprogrammable logic devices;

(b) providing a set of stimulus to said reconfigurable logic apparatus having the functional circuit configured therein;

(c) collecting a set of responses to said set of stimulus from said reconfigurable logic apparatus having the functional circuit configured therein; and

(d) converting said set of responses from a machine readable form to a user-readable form.

6. The method of claim 5 wherein said providing step comprises the steps of:

(a) converting said set of stimulus from a netlist format into a set of input vectors, said input vectors comprising binary data capable of loading into said N reprogrammable logic devices; and

(b) loading said binary data into said N reprogrammable logic devices.

7. The method of claim 5 wherein each step is performed in seriatim from step (a) to step (d).

8. The method of claim 5 wherein each of said N reprogrammable logic devices comprises a field programmable gate array.