Refresh circuit for DRAM with three-transistor type memory cells

• US 5,812,476 A
• Filed: 07/29/1997
• Issued: 09/22/1998
• Est. Priority Date: 07/30/1996
• Status: Expired due to Term

• Current Assignee: Kawasaki MicroElectronics (Megachips Corporation)
• Original Assignee: Kawasaki Steel Corporation (JFE Holdings Incorporated)
• Inventors: Segawa, Yuuichi
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NGUYEN, VAN THU T
• Application Number:
  US08/902,105
• Time in Patent Office: 420 Days
• Field of Search: 365/187, 365/188, 365/149, 365/150, 365/222, 365/230.05
• US Class Current: 365/222
• CPC Class Codes: G11C 11/406 Management or control of the refreshing or charge-regeneration cycles

Abstract

A semiconductor memory device of a three-transistor cell type dynamic random-access memory with improved performances includes a circuit arranged between a write bit line and a read bit line. During a read operation, the circuit generates a voltage difference responsive to information that is stored in the memory cell during a read operation. A latch-type sense amplifier amplifies and latches the voltage difference between the write bit line and the read bit line. When information is read from a memory cell, the information in the memory cell amplified by the latch-type sense amplifier is read through the read bit line while being written to the memory cell via the write bit line to refresh the information in the memory cell.

Claims

1. A three-transistor cell type dynamic random-access memory comprising:

a write bit line;

a read bit line;

a write word line;

a read word line;

a memory cell including a first transistor, a second transistor and a third transistor, wherein a drain of the first transistor is connected to the write bit line, a source of the first transistor is connected to a gate of the second transistor, a gate of the first transistor is connected to the write word line, a source of the second transistor is grounded, a drain of the second transistor is connected to a source of the third transistor, a drain of the third transistor is connected to the read bit line, and a gate of the third transistor is connected to the read word line;

a generating circuit arranged between the write bit line and the read bit line that generates a voltage difference, during a read operation, responsive to information that is stored in the memory cell; and

a sense amplifier that amplifies and latches the voltage difference generated between the write bit line and the read bit line, wherein when the information is read from the memory cell, the information from the memory cell amplified by the latch-type sense amplifier is read from the read bit line and is written to the memory cell via the write bit line to refresh the information in the memory cell.

2. The dynamic random-access memory according to claim 1, wherein the generating circuit includes a pre-charge circuit for pre-charging the write bit line and the read bit line to a substantially equal voltage, and a dummy cell for discharging the write bit line in response to a signal on a dummy word line.

3. The dynamic random-access memory according to claim 2, wherein the dummy cell includes a first NMOS transistor, a second NMOS transistor and a third NMOS transistor, wherein a drain of the first NMOS transistor is connected to the write bit line, a source of the first NMOS transistor is connected to a drain of the second NMOS transistor, a gate of the first NMOS transistor is connected to the dummy word line, a source of the second NMOS transistor is grounded, a gate of the second NMOS transistor is connected to a source of the third NMOS transistor, and a gate and a drain of the third NMOS transistor are both connected to a power supply.

4. The dynamic random-access memory according to claim 3, wherein the three transistors constituting the memory cell are each an NMOS transistor.

5. The dynamic random-access memory according to claim 1, wherein the circuit includes a differential voltage generating pre-charge circuit for pre-charging a differential voltage between the write bit line and the read bit line.

6. The dynamic random-access memory according to claim 5, wherein the differential voltage generating pre-charge circuit pre-charges the read bit line substantially to a power supply voltage, and pre-charges the write bit line to a voltage that is lower than the voltage of the read bit line.

7. The dynamic random-access memory according to claim 6, wherein the differential voltage generating pre-charge circuit sets the voltage of the write bit line to be lower than the voltage of the read bit line by the threshold voltage of the MOS transistor.

8. A semiconductor integrated circuit comprising a three-transistor cell type dynamic random-access memory comprising:

a write bit line;

a read bit line;

a write word line;

a read word line;

a memory cell including a first transistor, a second transistor and a third transistor, wherein a drain of the first transistor is connected to the write bit line, a source of the first transistor is connected to a gate of the second transistor, a gate of the first transistor is connected the write word line, a source of the second transistor is grounded, a drain of the second transistor is connected to a source of the third transistor, and a drain of the third transistor is connected to the read bit line, a gate of the third transistor is connected to the read word line;

a generating circuit arranged between the write bit line and the read bit line that generates a voltage difference, during a read operation, responsive to information that is stored in the memory cell;

a sense amplifier that amplifies and latches the voltage difference generated between the write bit line and the read bit line, wherein when the information is read from the memory cell, the information from the memory cell amplifier by the latch-type sense amplifier is read from the read bit line and is written to the memory cell via the write bit line to refresh the information in the memory cell.

9. The semiconductor integrated circuit according to claim 8, wherein the generating circuit including a pre-charge circuit for pre-charging the write bit line and the read bit line to a substantially identical voltage, and a dummy cell for discharging the write bit line in response to a signal on a dummy word line.

10. The semiconductor integrated circuit according to claim 9, wherein the dummy cell including a first NMOS transistor, a second NMOS transistor, and a third NMOS transistor, wherein a drain of the first transistor is connected to the write bit line, a source of the first transistor is connected to a drain of the second transistor, a gate of the first transistor is connected to the dummy word line, a source of the second transistor is grounded, a gate of the second transistor is connected to a source of the third transistor, and a gate and a drain of the third transistor are both connected to a power supply.

11. The semiconductor integrated circuit according to claim 10, wherein the three transistors constituting the memory cell are each an NMOS transistor.

12. The semiconductor integrated circuit according to claim 11, wherein the generating circuit includes a differential voltage generating pre-charge circuit for pre-charging a differential voltage between the write bit line and the read bit line.

13. The semiconductor integrated circuit according to claim 12, wherein the differential voltage generating pre-charge circuit pre-charges the read bit line substantially to a power supply voltage, and pre-charges the write bit line to a voltage that is lower than the voltage of the read bit line.

14. The semiconductor integrated circuit according to claim 13, wherein the differential voltage generating pre-charge circuit sets the voltage of the write bit line to be lower than the voltage of the read bit line by the threshold voltage of the MOS transistor.