Synchronous burst extended data out dram

• US 5,812,488 A
• Filed: 03/05/1997
• Issued: 09/22/1998
• Est. Priority Date: 12/23/1994
• Status: Expired due to Term

• Current Assignee: Round Rock Research LLC
• Original Assignee: Micron Technology, Inc.
• Inventors: Merritt, Todd, Manning, Troy A., Zagar, Paul S.
• Primary Examiner(s): NGUYEN, TAN
• Application Number:
  US08/811,696
• Time in Patent Office: 566 Days
• Field of Search: 365/233, 365/233.5, 365/238.5, 365/236, 395/855
• US Class Current: 365/233.13
• CPC Class Codes: G06F 12/0638 Combination of memories, e.g. ROM and RAM such as to permit replacement or supplementing of words in one module by words in another module address formation of the next microinstruction G06F9/26; masking faults in memories by using spares or by reconfiguring G11C29/70
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 11/407 for memory cells of the field-effect type
• CPC Class Codes: G11C 7/1018 Serial bit line access mode, e.g. using bit line address shift registers, bit line address counters, bit line burst counters
• CPC Class Codes: G11C 7/1021 Page serial bit line access mode, i.e. using an enabled row address stroke pulse with its associated word line address and a sequence of enabled column address stroke pulses each with its associated bit line address
• CPC Class Codes: G11C 7/1024 Extended data output [EDO] mode, i.e. keeping output buffer enabled during an extended period of time
• CPC Class Codes: G11C 7/1039 using pipelining techniques, i.e. using latches between functional memory parts, e.g. row/column decoders, I/O buffers, sense amplifiers
• CPC Class Codes: G11C 7/1045 Read-write mode select circuits
• CPC Class Codes: G11C 7/1072 for memories with random access ports synchronised on clock signal pulse trains, e.g. synchronous memories, self timed memories
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/109 Control signal input circuits
• CPC Class Codes: G11C 7/1096 Write circuits, e.g. I/O line write drivers

Abstract

An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. A clock signal is provided to synchronize the burst operations. The clock signal is independent of an address latch signal used to latch an external address.

Claims

1. A memory device comprising:

a plurality of addressable memory elements;

addressing circuitry adapted to receive a first memory element address in response to a transition of a clock signal and an address latch signal, and further adapted to generate a second memory element address in response to a subsequent transition of the clock signal, wherein the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and

output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.

2. A synchronous memory device comprising:

a memory array having a plurality of addressable memory elements;

a plurality of address inputs for receiving memory element addresses;

an address latch input for receiving an address latch signal;

an address latch for receiving a first memory element address in response to a transition of a clock signal and the address latch signal;

an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses, the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and

output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.

3. A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:

receiving a first memory element address in response to a transition of a clock signal and an address latch signal; and

generating additional memory element addresses in response to subsequent transitions of the clock signal, wherein the first memory element address is received in response to a rising transition of the clock signal when the address latch signal is at a low voltage level;

receiving an output enable signal; and

asynchronously controlling data output from the synchronous memory device in response to the output enable signal.

4. A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:

receiving a first memory element address in response to a transition of a clock signal and an address latch signal;

accessing first memory elements having the first memory element address;

generating additional memory element addresses in response to subsequent transitions of the clock signal;

accessing additional memory elements having the additional memory element addresses;

receiving an output enable signal; and

asynchronously controlling data output from the synchronous memory device in response to the output enable signal.

5. A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:

receiving a first memory element address in response to a transition of a clock signal and an address latch signal;

accessing first memory elements having the first memory element address;

generating additional memory element addresses in response to subsequent transitions of the clock signal;

accessing additional memory elements having the additional memory element addresses;

synchronously reading a memory array row address in response to an active row access signal (RAS\);

synchronously reading a memory array column address in response to an active column access signal (CAS\);

receiving an output enable signal; and

asynchronously controlling data output from the synchronous memory device in response to the output enable signal.

6. A synchronous memory device comprising:

a memory array having a plurality of addressable memory elements;

a plurality of address inputs for receiving memory element addresses;

an address latch input for receiving an address latch signal;

an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; and

an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state,

the address generation circuit including a counter circuit coupled to the address latch to enable the address latch to receive a new address from the plurality of address inputs after a predetermined number of access cycles.

7. A synchronous memory device comprising:

a memory array having a plurality of addressable memory elements;

a plurality of address inputs for receiving memory element addresses;

an address latch input for receiving an address latch signal;

an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal;

an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and

the first memory element address is received on a rising edge of the clock signal when the address latch signal is low.

8. A synchronous memory device comprising:

a memory array having a plurality of addressable memory elements;

a plurality of address inputs for receiving memory element addresses;

an address latch input for receiving an address latch signal;

an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal;

an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and

the additional memory element addresses are generated on rising edges of the clock signal.

9. A synchronous memory device comprising:

a memory array having a plurality of addressable memory elements;

a plurality of address inputs for receiving memory element addresses;

an address latch input for receiving an address latch signal;

an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal;

an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and

an output buffer circuit adapted to drive data from the synchronous memory device, and further adapted to switch between data values in response to a falling transition of the clock signal.

10. A synchronous memory device comprising:

a memory array having a plurality of addressable memory elements;

a plurality of address inputs for receiving memory element addresses;

an address latch input for receiving an address latch signal;

an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal;

an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and

a write enable input for receiving a write enable signal, and adapted to switch between read and write access cycles of the synchronous memory device and to terminate a burst access of the memory array.

11. A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:

receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; and

generating additional memory element addresses in response to subsequent transitions of the clock signal and while the address latch signal is in an inactive state, wherein the first memory element address is received in response to a rising transition of the clock signal when the address latch signal is at a low voltage level.

12. A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:

receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; and

generating additional memory element addresses in response to subsequent transitions of the clock signal while the address latch signal is in an inactive state.

13. The method of claim 12 further wherein the additional memory element addresses are generated in response to subsequent rising edges of the clock signal.

14. The method of claim 12 further including the step of:

outputting data stored at the first and additional memory element addresses in response to the clock signal.

15. The method of claim 12 further including the step of:

storing data at the first and additional memory element addresses in response to the clock signal.

16. A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:

receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal;

accessing first memory elements having the first memory element address;

generating additional memory element addresses in response to subsequent transitions of the clock signal while the address latch signal is in an inactive state; and

accessing additional memory elements having the additional memory element addresses.

17. The method of claim 16 further comprising the steps of:

storing data at the first memory elements; and

storing data at the additional memory elements.

18. The method of claim 16 further comprising the steps of:

reading data stored at the first memory elements; and

reading data stored data at the additional memory elements.