Synchronous burst extended data out dram
First Claim
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1. A memory device comprising:
- a plurality of addressable memory elements;
addressing circuitry adapted to receive a first memory element address in response to a transition of a clock signal and an address latch signal, and further adapted to generate a second memory element address in response to a subsequent transition of the clock signal, wherein the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and
output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.
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Abstract
An integrated circuit memory device is described which can operate at high data speeds. The memory device can either store or retrieve data from the memory in a burst access operation. The burst operations latches a memory address from external address lines and internally generates additional memory addresses. A clock signal is provided to synchronize the burst operations. The clock signal is independent of an address latch signal used to latch an external address.
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Citations
18 Claims
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1. A memory device comprising:
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a plurality of addressable memory elements; addressing circuitry adapted to receive a first memory element address in response to a transition of a clock signal and an address latch signal, and further adapted to generate a second memory element address in response to a subsequent transition of the clock signal, wherein the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.
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2. A synchronous memory device comprising:
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a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses, the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.
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3. A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:
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receiving a first memory element address in response to a transition of a clock signal and an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal, wherein the first memory element address is received in response to a rising transition of the clock signal when the address latch signal is at a low voltage level; receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
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4. A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:
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receiving a first memory element address in response to a transition of a clock signal and an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal; accessing additional memory elements having the additional memory element addresses; receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
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5. A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:
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receiving a first memory element address in response to a transition of a clock signal and an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal; accessing additional memory elements having the additional memory element addresses; synchronously reading a memory array row address in response to an active row access signal (RAS\); synchronously reading a memory array column address in response to an active column access signal (CAS\); receiving an output enable signal; and asynchronously controlling data output from the synchronous memory device in response to the output enable signal.
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6. A synchronous memory device comprising:
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a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; and an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state, the address generation circuit including a counter circuit coupled to the address latch to enable the address latch to receive a new address from the plurality of address inputs after a predetermined number of access cycles.
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7. A synchronous memory device comprising:
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a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and the first memory element address is received on a rising edge of the clock signal when the address latch signal is low.
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8. A synchronous memory device comprising:
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a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and the additional memory element addresses are generated on rising edges of the clock signal.
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9. A synchronous memory device comprising:
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a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and an output buffer circuit adapted to drive data from the synchronous memory device, and further adapted to switch between data values in response to a falling transition of the clock signal.
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10. A synchronous memory device comprising:
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a memory array having a plurality of addressable memory elements; a plurality of address inputs for receiving memory element addresses; an address latch input for receiving an address latch signal; an address latch for receiving a first memory element address in response to a transition of a clock signal and an active state of the address latch signal; an address generation circuit responsive to successive transitions of the clock signal and to the first memory element address for generating additional memory element addresses while the address latch signal is in an inactive state; and a write enable input for receiving a write enable signal, and adapted to switch between read and write access cycles of the synchronous memory device and to terminate a burst access of the memory array.
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11. A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:
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receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal and while the address latch signal is in an inactive state, wherein the first memory element address is received in response to a rising transition of the clock signal when the address latch signal is at a low voltage level.
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12. A method of accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:
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receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; and generating additional memory element addresses in response to subsequent transitions of the clock signal while the address latch signal is in an inactive state. - View Dependent Claims (13, 14, 15)
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16. A method of burst accessing a memory device having a plurality of addressable memory elements, the method comprising the steps of:
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receiving a first memory element address in response to a transition of a clock signal and an active state of an address latch signal; accessing first memory elements having the first memory element address; generating additional memory element addresses in response to subsequent transitions of the clock signal while the address latch signal is in an inactive state; and accessing additional memory elements having the additional memory element addresses. - View Dependent Claims (17, 18)
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Specification