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Synchronous burst extended data out dram

  • US 5,812,488 A
  • Filed: 03/05/1997
  • Issued: 09/22/1998
  • Est. Priority Date: 12/23/1994
  • Status: Expired due to Term
First Claim
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1. A memory device comprising:

  • a plurality of addressable memory elements;

    addressing circuitry adapted to receive a first memory element address in response to a transition of a clock signal and an address latch signal, and further adapted to generate a second memory element address in response to a subsequent transition of the clock signal, wherein the first memory element address is received on a rising edge of the clock signal when the address latch signal is low; and

    output enable circuitry for asynchronously preventing data output from the memory device in response to an externally provided output enable signal.

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