Scan based testing of an integrated circuit for compliance with timing specifications

• US 5,812,561 A
• Filed: 09/03/1996
• Issued: 09/22/1998
• Est. Priority Date: 09/03/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Marquette, Daniel T., Doege, Jason E., Giles, Grady L., Crouch, Alfred Larry, Amason, Jr., Odis Dale, Pressly, Matthew Donald, Shepard, Clark Gilson, Mateja, Michael Alan, Corley, Lee Allen
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/707,272
• Time in Patent Office: 749 Days
• Field of Search: 371/22.31, 371/22.32, 371/22.34, 371/22.36, 371/22.5, 371/25.1, 371/27.7, 371/27.4, 364/488, 364/489, 364/578, 395/183.06, 395/183.09, 395/183.19, 395/500, 395/550, 395/182.06, 324/73.1
• US Class Current: 714/726
• CPC Class Codes: G01R 31/318572 Input/Output interfaces
• CPC Class Codes: G01R 31/31858 Delay testing

Abstract

A method and implementation for providing an improved testable design for an integrated circuit (IC) device. The integrated circuit includes a functional path for the implementation of a functional specification as well as a testing path for testing the timing specifications for the integrated circuit. Input switching devices are connected between input terminals of the IC and inputs to sequential circuit elements, for example flip-flop devices, in the IC. Similarly, output switching devices are connected between outputs of the flip-flop devices and output terminals of the IC. The switching devices are selectively operable to alternately connect the flip-flop devices into either a functional IC path for providing functional output signals during functional cycles, or into a testing IC path for providing testing output signals indicative of timing points throughout the IC during testing cycles. The IC is also operable to selectively disable tristate bus drivers during the testing cycles. The switching devices are arranged such that a single output terminal of the IC may be selectively used to provide both functional and testing output signals.

Claims

1. A method for testing timing specifications for an integrated circuit, said integrated circuit having functional circuit paths including sequential circuit elements therein, said functional circuit paths being designed to implement a specified functional specification and provide functional output signals at output terminals of said integrated circuit, said method comprising the steps of:

providing a scan path on said integrated circuit, said scan path being selectively routed on said integrated circuit among selected sequential circuit elements, said scan path being terminated at said integrated circuit output terminals, said integrated circuit input/output terminals also being arranged to selectively provide functional output signals for said functional circuit paths;

applying a first testing signal to said integrated circuit, said first testing signal being operable to effect a testing signal propagation through said scan path and provide a timing output signal at one of said integrated circuit output terminals; and

applying a second testing signal to said integrated circuit, said second testing signal being applied independently of the first testing signal and independently of the sequential circuit elements, the second testing signal operable to control when the output terminal is used to provide the functional output signals and when the output terminal is used to provide the timing output signal.

2. The method as set forth in claim 1 and further including validating said timing output signal from said integrated circuit output terminals.

3. The method as set forth in claim 2, wherein said sequential circuit element is a latching circuit.

4. The method as set forth in claim 2, wherein said sequential circuit element is a flip-flop circuit.

5. The method as set forth in claim 2, wherein said method further includes:

switching from said scan path to said functional circuit path following said validating of said timing output signal.

6. The method as set forth in claim 2, wherein said method further includes:

switching from said functional circuit path to said scan path following a predetermined delay time of said timing output signal.

7. The method as set forth in claim 2, wherein said integrated circuit further includes at least one tristate device for driving at least one signal line, said method further including selectively enabling and disabling said tristate device during said testing signal propagation.

8. An integrated circuit comprising:

a plurality of input terminals;

a plurality of output terminals;

logic circuitry connected between said input terminals and said output terminals, said logic circuitry defining a functional circuit path, said logic circuitry including at least one sequential circuit element, said logic circuitry being selectively operable to implement a functional specification for said integrated circuit through a functional circuit path to provide functional output signals at said output terminals; and

testing signal circuitry connected between said input terminals and said output terminals, said testing signal circuitry defining a testing circuit path, a scan enable signal being applied to said test signal circuitry for controlling shifting of the test data through said testing circuit path, said testing signal circuitry further including a first switching device connecting one of said input terminals to an input terminal of said sequential circuit element, and a second switching device connecting an output terminal of said sequential circuit element to one of said integrated circuit output terminals, said first switching device and said second switching device being controlled by a bus scan enable signal, the bus scan enable signal being applied independently of both the scan enable signal and the at least one sequential circuit element, the bus scan enable signal is operable to control when the plurality of input terminals are used to receive the functional input signals, and to control when the plurality of output terminals are to provide the functional output signals, and to control when the plurality of output terminals are to provide the test data, wherein the use of bus scan enable signal is for implementing a timing analysis of the integrated circuit.

9. The integrated circuit as set forth in claim 8, wherein said first and second switching devices are selectively operable to switch between a first position effective to complete said functional circuit path between said input terminals and said output terminals, and a second position effective to complete said testing circuit between said input terminals and said output terminals path during a testing cycle.

10. The integrated circuit as set forth in claim 9, wherein said functional circuit path further includes at least one tristate device arranged to selectively drive at least one signal line, said integrated circuit further including a signal generating device for generating a disable signal, said disable signal being effectively applied to said tristate device to selectively disable said tristate device during said testing signal propagation.

11. The integrated circuit as set forth in claim 8, wherein said second switching device is selectively operable to connect said output terminal of said sequential circuit element to a shared output terminal of said integrated circuit, said shared output terminal being arranged to be selectively connected to provide an output signal from said functional circuit path and from said testing circuit path.

12. The integrated circuit as set forth in claim 9, wherein said second switching device is selectively operable to connect said output terminal of said sequential circuit element to a shared output terminal of said integrated circuit, said shared output terminal being arranged to be selectively connected to provide an output signal from said functional circuit path and from said testing circuit path.

13. The integrated circuit as set forth in claim 10, wherein said second switching device is selectively operable to connect said output terminal of said sequential circuit element to a shared output terminal of said integrated circuit, said shared output terminal being arranged to be selectively connected to provide an output signal from said functional circuit path and from said testing circuit path.

14. The integrated circuit as set forth in claim 13, wherein said shared output terminal is a bidirectional terminal for providing an input signal to said functional circuit path.

15. The integrated circuit as set forth in claim 8, wherein said first switching device is a multiplexer, said multiplexer circuit being arranged to selectively connect said sequential circuit element into said functional circuit path or said testing circuit path.

16. The integrated circuit as set forth in claim 8, wherein said second switching device is a multiplexer, said multiplexer circuit being arranged to selectively connect said sequential circuit element into said functional circuit path or said testing circuit path.

17. The integrated circuit as set forth in claim 15, wherein said second switching device is a multiplexer, said multiplexer circuit being arranged to selectively connect said sequential circuit element into said functional circuit path or said testing circuit path.

18. The integrated circuit as set forth in claim 8, wherein said integrated circuit includes a plurality of sequential circuit elements, said integrated circuit further including a like plurality of each of said first and second switching devices connected to said sequential circuit elements.

19. The integrated circuit as set forth in claim 8, wherein said testing signal circuitry further includes a head register device connected between said one of said input terminals and said input terminal of said sequential element.

20. The integrated circuit as set forth in claim 19, wherein said head register device is comprised of at least one head register sequential logic device.

21. The integrated circuit as set forth in claim 20, wherein said head register sequential logic device is comprised of at least one flip-flop circuit.

22. The integrated circuit as set forth in claim 19, wherein said testing signal circuitry further includes a tail register device connected at an end of the testing circuit path for adding delay time for the testing circuit path.