Circuit board testing

• US 5,812,563 A
• Filed: 06/27/1997
• Issued: 09/22/1998
• Est. Priority Date: 06/28/1996
• Status: Expired due to Term

• Current Assignee: Optis Wireless Technology, LLC (Brevet Capital)
• Original Assignee: Telefonaktiebolaget LM Ericsson
• Inventors: Hogberg, Hans, Hedlund, Mikael
• Primary Examiner(s): Canney, Vincent P.
• Application Number:
  US08/883,904
• Time in Patent Office: 452 Days
• Field of Search: 371/27.1, 371/27.3, 371/27.5, 371/28, 371/22.1, 324/73 R, 324/73 AI
• US Class Current: 714/738
• CPC Class Codes: G01R 31/2803 by means of functional tests, e.g. logic-circuit-simulation or algorithms therefor testing electronic digital computers G06F11/00

Abstract

A method and arrangement for testing circuit boards (60) by creating one or several reference patterns to be compared with a test pattern. The arrangement is provided with at least one measuring probe (50), which cooperates with the circuit board (60), for measuring at least one reference signal or test signal on a reference circuit board and a test circuit board (60) respectively. Further, the arrangement is provided with an analyzer (10,30), which cooperates with the measuring probe (50), to pass on the reference signal or the test signal, whereby the analyzer (10,30) first analyzes the reference signal or the test signal at one frequency and then transforms the reference signal or the test signal to a reference pattern and test pattern respectively. Furthermore, the arrangement is provided with at least one memory (20) which cooperates with said analyzer (10,30) to register said reference pattern or test pattern. The memory (20) is provided with two or several reference patterns when testing a circuit board (60).

Claims

1. A method for testing circuit boards (60) which method comprises the following steps for creating a reference pattern:

a1) measuring at least one reference signal on a reference circuit board (60) by means of at least one measuring probe (50) which is connected to said circuit board (60),

b1) transmitting the reference signal by means of said measuring probe (50) to an analyzer (10,30),

c1) in which said analyzer (10,30) first analyzes said reference signal at at least one frequency and then converts said reference signal to a reference pattern,

d1) registering said reference pattern in at least one memory (20) which is connected to said analyzer (10,30),

and which method further comprises the following steps for testing a circuit board which is to be tested (60);

a2) measuring at least one test signal on a circuit board (60) which is to be tested by means of at least one measuring probe (50) which is connected to said circuit board (60) which is to be tested,

b2) transmitting the test signal by means of said measuring probe (50) to an analyzer (10,30),

c2) where said analyzer (10,30) first analyzes said test signal at at least one frequency and then converts said test signal to a test pattern,

d2) comparing said test pattern with said reference pattern,

in which the reference pattern and the test pattern are characterized by separate sets of values, characterized in that the values of the test pattern are compared with the set of values of the reference pattern in order to estimate the difference between the reference pattern and the test pattern.

2. Method according to claim 1, characterized in that said memory (20) further comprises information regarding the condition of the reference circuit board (60).

3. Method according to claim 2, characterized in that said information comprises symptoms and/or causes of faults.

4. Method according to claim 2, characterized in that said information is transmitted to an output unit.

5. Method according to claim 1, characterized in that said reference pattern consists of an average from a plurality of circuit boards.

6. Method according to claim 1, characterized in that said signals are measured at a plurality of different frequencies.

7. Method according to claim 1, characterized in that said measuring probe is a field probe and/or a galvanic probe.

8. Method according to claim 1, characterized in that said steps for creating a reference pattern is repeated on different reference boards (60), and a plurality of reference patterns is obtained which is stored in said memory (20).

9. Method according to claim 8, characterized in that said test pattern is compared with different reference patterns.

10. Method according to claim 9, characterized in that the method can be carried out iteratively.

11. Method according to claim 1, characterized in that said signals are dynamical.

12. Method according to claim 1, characterized in that said memory (20) is arranged either internally or externally on said analyzer (10,30).

13. An arrangement for testing circuit boards (60), which arrangement comprises the following components for creating a reference pattern or a test pattern:

1) at least one measuring probe (50) which is connected to said circuit board (60) for measuring at least one reference signal or test signal on a reference circuit board or a circuit board (60) which is to be tested,

2) an analyzer (10,30) which is connected to said measuring probe (50) in order to transmit the reference signal or test signal, where said analyzer (10,30) first analyzes said reference signal or the test signal at one frequency, and then converts said reference signal or the test signal to a reference pattern respectively a test pattern,

3) at least one memory (20) which is connected to said analyzer (10,30) in order to register said reference pattern or test pattern,

in which said memory (20) is arranged with one or several reference patterns during a test of a circuit board (60), where the reference patterns comprise a plurality of different sets of values, and in which the reference pattern comprises a set of values, characterized in that said arrangement is equipped with means for estimating the difference between one of the reference patterns and the test pattern, in order to compare the values of the test pattern with one or several of the different sets of values of the reference pattern.