Digital receiver using a concatenated decoder with error and erasure correction

• US 5,812,603 A
• Filed: 08/22/1996
• Issued: 09/22/1998
• Est. Priority Date: 08/22/1996
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Bhaskaran, Ravi, Mogre, Advait M., Rhee, Dojun, Luthi, Daniel A.
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Roundtree, Joseph
• Application Number:
  US08/701,632
• Time in Patent Office: 761 Days
• Field of Search: 371/20.4, 371/20.5, 371/37.01, 371/43, 371/43.1, 371/43.7, 371/45, 375/340, 375/341, 375/287
• US Class Current: 375/287
• CPC Class Codes: H04L 1/0045 Arrangements at the receiver end
• CPC Class Codes: H04L 1/0057 Block codes H04L1/0061, H04L1/0064 take precedence
• CPC Class Codes: H04L 1/0065 Serial concatenated codes
• CPC Class Codes: H04L 1/0071 Use of interleaving interleaving per se H03M13/27

Abstract

A communications receiver system is presented for detecting burst errors and providing erasure information to the block decoder, thereby effectively doubling the conventional correction capability of the block decoder with only a minimal increase in complexity. In one embodiment, this mechanism takes the form of a circuit which re-encodes the output of the inner decoder, compares it with the received sequence of code symbols, and flags a portion of the inner decoder output for erasure when an excessive number of code symbol errors are detected. In a second embodiment, this mechanism takes the form of a circuit which makes hard symbol decisions on the channel signal, compares the hard decisions to the channel signal to determine a noise level, and thereafter flags the channel output in regions with excessive noise levels.

Claims

1. A digital communications system comprising:

an encoder configured to receive a digital signal and thereafter convert said digital signal to a coded digital signal;

a transmission channel through which said coded digital signal is transmitted;

an inner convolutional decoder coupled to said transmission channel and an outer block decoder coupled to said inner convolutional decoder, wherein the combination of said inner and outer decoders are configured to convert said coded digital signal to substantially said digital signal; and

an error detector coupled to both said transmission channel and said inner convolutional decoder for inserting error flags within an intermediate coded digital signal indicative of the presence of errors within said intermediate coded digital signal forwarded from said inner convolutional decoder to said outer block decoder, wherein said error detector comprises

an inner encoder coupled to an output of said inner convolutional decoder; and

a comparator coupled to receive an output of said inner encoder and said transmission channel, and to compare the output of the inner encoder with the output of said transmission channel to determine the presence of said errors within said intermediate coded digital signal.

2. The digital communications system as recited in claim 1, further comprising:

an interleaver coupled within said encoder; and

a de-interleaver coupled between said inner convolutional decoder and said outer block decoder for producing a de-interleaved signal which is substantially the same as a signal forwarded to said interleaver.

3. The digital communications system as recited in claim 2, wherein said error flags are set in each of multiple locations within a region of said intermediate coded digital signal, wherein said multiple locations are adjacent within said intermediate coded digital signal prior to entry into said de-interleaver and are separated within said de-interleaved signal after exit from said de-interleaver.

4. The digital communications system as recited in claim 1, wherein said transmission channel is a satellite transmission channel.

5. The digital communications system as recited in claim 1, wherein said error detector further comprises a threshold detector operably coupled to a filter which in turn is coupled to receive output from said comparator, said filter is configured to determine a number of symbol errors in a predefined interval, and said threshold detector is configured to set a flag indicating whether said number of symbol errors exceeds a threshold value.

6. An apparatus for detecting errors within a decoded sequence of symbols, comprising:

a de-interleaver interposed between an inner decoder and an outer decoder;

a comparator having two inputs, wherein one of said two inputs is coupled to receive a coded sequence of symbols input to said inner decoder and the other of said two inputs is coupled to receive a benchmark sequence of symbols produced by re-encoding said decoded sequence of symbols output from said inner decoder; and

a mechanism coupled to an output of said comparator for determining a number of symbols within said coded sequence of symbols which are dissimilar to said benchmark sequence of symbols and setting a flag whenever said number of symbols exceeds a threshold amount in a predefined interval.

7. The apparatus as recited in claim 6, wherein said flag is set in a location of said decoded sequence of symbols which resulted from decoding a portion of said coded sequence of symbols in which said symbol is dissimilar from said benchmark symbol after said number exceeds the threshold amount.

8. The apparatus as recited in claim 7, wherein said flag is indicative of a mismatch between symbols within said coded sequence of symbols and symbols within said benchmark sequence of symbols.

9. The apparatus as recited in claim 6, wherein said flag is set in each of multiple locations within a region of said decoded sequence of symbols corresponding to multiple mismatches between symbols within said sequence of symbols and symbols within said benchmark sequence of symbols.

10. The apparatus as recited in claim 9, wherein said multiple locations are adjacent within said sequence of symbols prior to entry into said de-interleaver and are separated within said sequence of symbols after exit from said de-interleaver.

11. The apparatus as recited in claim 6, wherein said flag may be set in multiple locations of said code word at approximately twice the quantity of erroneous symbols correctable by an apparatus absent said comparator.

12. A method for locating erroneous symbols within a decoded sequence of symbols, comprising:

comparing symbols within a code word output from a channel to benchmark symbols approximating a code word forwarded to said channel;

setting a flag within a said code word identifying locations of erroneous symbols which are dissimilar from said benchmark symbols; and

forwarding said flag along with said code word to a block decoder in order to correct said erroneous symbols at a rate greater than that afforded if said setting and said forwarding of the flag are not achieved.

13. The method for locating erroneous symbols within a decoded sequence of symbols as recited in claim 12, wherein said channel is a discrete time channel.