Synchronization and battery saving technique

• US 5,812,617 A
• Filed: 12/28/1994
• Issued: 09/22/1998
• Est. Priority Date: 12/28/1994
• Status: Expired due to Fees

• Current Assignee: Mobile Knowledge, Inc.
• Original Assignee: Silcom Research Limited
• Inventors: Panther, Gyles, Heckman, John Benjamin
• Primary Examiner(s): Bocure, Tesfaldet
• Assistant Examiner(s): WEBSTER, BRYAN E
• Application Number:
  US08/365,505
• Time in Patent Office: 1,364 Days
• Field of Search: 375/362, 375/354, 375/365, 375/366, 375/368, 375/373, 375/376, 375/364, 370/100.1, 370/105.4, 370/105.5, 370/105.6, 340/825.44, 340/311.1, 455/38.3, 455/343
• US Class Current: 375/362
• CPC Class Codes: H03L 7/0802 the loop being adapted for reducing power consumption H03L7/14 takes precedence
• CPC Class Codes: H03L 7/095 using a lock detector H03L7/087 takes precedence
• CPC Class Codes: H03L 7/0993 and a circuit for adding and deleting pulses
• CPC Class Codes: H03L 7/107 using a variable transfer function for the loop, e.g. low pass filter having a variable bandwidth
• CPC Class Codes: H04B 1/1615 Switching on; Switching off, e.g. remotely battery saving circuits associated with selective call operation H04W52/00; details of power consumption reduction in a PLL, H03L7/0802, H03L7/14, H03L2207/08, H03L2207/18; muting amplifiers by gain control see H03G3/34
• CPC Class Codes: H04L 7/0083 taking measures against momentary loss of synchronisation, e.g. inhibiting the synchronisation, using idle words or using redundant clocks
• CPC Class Codes: H04L 7/0331 with a digital phase-locked loop [PLL] processing binary samples, e.g. add/subtract logic for correction of receiver clock H04L7/0337 takes precedence
• CPC Class Codes: H04W 52/0229 where the received signal is a wanted signal
• CPC Class Codes: H04W 88/022 Selective call receivers
• CPC Class Codes: Y02D 30/70 in wireless communication networks

Abstract

A synchronization apparatus in a selective call receiver comprised of a digital variable bandwidth phase locked loop with means to simultaneously detect the synchronization code word, means to generate a binary code from a register representative of lock quality, means to increment or decrement the lock quality register, means to sum the lock quality binary code into a phase error register, whereby the polarity of the sum is controlled by a phase comparison of the a local clock with the received data, and whereby the under or over flow of the phase error register determines the direction of a phase adjustment to the local bit clock generator.

Claims

1. A synchronization method in a selective call receiver comprised of a radio receiver, microcontroller, and a digital phase locked loop, whereby synchronization of the local bit clock with a received data stream is achieved by the steps of:

a) periodically enabling the radio receiver to receive and demodulate a wanted RF signal for a first sampling period with a sampling interval of a first time period

b) generating a received data transition signal from the receiver output such that each transition of a selected direction in a received digital signal is represented by single pulse

c) enabling a digital phase locked loop simultaneously with the enabled period of the radio receiver so as to potentially acquire bit synchronization with the said received data transition signal, if received,

d) extending the enable time for the radio and digital phase locked loop for a second time period if the digital phase locked loop becomes locked to the received data transition signal

e) simultaneously searching for a pre-determined synchronization code word for the duration of the radio enable time

f) repeating steps d and e if the digital phase locked loop becomes locked but no sync code word is detected, and

g) enabling the radio receiver and phase locked loop after a third time period said third time period being shorter than said first time period, if the digital phase locked loop fails to remain locked after having initially becoming locked in any immediately preceding occurrence of step c.

2. A synchronization method in a selective call receiver comprised of a radio receiver, microcontroller, and a digital phase locked loop, whereby synchronization of the local bit clock with a received data stream is achieved by the steps of:

a) periodically enabling the radio receiver to receive and demodulate a wanted RF signal for a first sampling period with a sampling interval of a first time period

b) generating a received data transition signal from the receiver output such that each transition of a selected direction in a received digital signal is represented by single pulse

c) enabling a digital phase locked loop simultaneously with the enabled period of the radio receiver so as to potentially acquire bit synchronization with the said received data transition signal, when received,

d) extending the enable time for the radio and digital phase locked loop for a second time period if the digital phase locked loop becomes locked to the received data transition signal

e) simultaneously searching for a pre-determined synchronization code word for the duration of the radio enable time

f) synchronizing digital data codeword timing logic with the received data transition signal on detection of the synchronization code word

e) evaluating subsequently repeated occurrences of the synchronization code word only in response to detection of errors in decoding selected digital data codewords, and

f) immediately re-attempting acquisition of bit and batch synchronization on failure to detect the synchronization code word at the expected time.

3. A synchronization apparatus in a selective call receiver including means for simultaneously detecting a synchronization code word and a variable bandwidth digital phase lock loop, the variable bandwidth digital phase lock loop comprising:

a lock quality register;

a phase error register having overflow and underflow outputs;

a local clock;

means for deriving a clock transition window from the local clock;

a phase detector having inputs for a received data transition signal derived from a received data signal and local clock and an output;

means for generating a binary code from the lock quality register;

means for incrementing or decrementing the lock quality register in dependence upon the output of the phase detector and the clock transition window;

means for summing the binary code into the phase error register wherein the polarity of summing is dependent upon the output of the phase detector; and

means responsive to the overflow and underflow output of the phase error register for effecting a phase adjustment of the local clock.

4. A synchronization method in a selective call receiver comprised of a radio receiver, microcontroller, and a digital phase locked loop, whereby synchronization of the local bit clock with a received data stream is achieved by the steps of:

a) periodically enabling the radio receiver to receive and demodulate a wanted RF signal for a first sampling period with a sampling interval of a first time period

b) generating a received data transition signal from the receiver output such that each transition of a selected direction in a received digital signal is represented by single pulse

c) enabling a digital phase locked loop simultaneously with the enabled period of the radio receiver so as to potentially acquire bit synchronization with the said received data transition signal, if received

d) extending the enable time for the radio and digital phase locked loop for a second time period if the digital phase locked loop becomes locked to the received data transition signal

e) simultaneously searching for a pre-determined synchronization code word for the duration of the radio enable time

f) repeating steps d and e if the digital phase locked loop becomes locked but no sync code word is detected, and

g) enabling the radio receiver and phase locked loop after a third time period said third time period being shorter than said first time period, if the digital phase locked loop fails to remain locked after having initially becoming locked in any immediately preceding occurrence of step d.