Method and apparatus for internetworking buffer management

• US 5,812,775 A
• Filed: 07/12/1995
• Issued: 09/22/1998
• Est. Priority Date: 07/12/1995
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: 3Com Corporation (HP Inc.)
• Inventors: Hauser, Stephen A., Sankey, Mark A., Van Seters, Stephen L., Lawler, Christopher P.
• Primary Examiner(s): Lall, Parshotam S.
• Assistant Examiner(s): Coulter, Kenneth R.
• Application Number:
  US08/501,355
• Time in Patent Office: 1,168 Days
• Field of Search: 395/200.45, 395/200.43, 395/200.44, 395/479, 395/480, 395/481, 395/483, 711/153
• US Class Current: 709/213
• CPC Class Codes: H04L 49/90 Buffering arrangements
• CPC Class Codes: H04L 49/901 using storage descriptor, e.g. read or write pointers
• CPC Class Codes: H04L 49/9047 including multiple buffers, e.g. buffer pools
• CPC Class Codes: H04L 69/12 Protocol engines

Abstract

A method and apparatus for receiving and transmitting network frames via an internetworking device, in which a first portion of a total number of buffers is allocated among port-dedicated buffer pools, and a second portion is placed in a common pool accessible by any of the network ports. A frame is received at a first port, and a list of buffers accessible only by that port is referenced to identify buffers not already in use. A second list of buffers in the common pool is referenced to identify unused buffers for use if insufficient unused buffer space is available in the port-dedicated buffer pool. Frame data is then stored in the identified buffer(s). Upon retransmission, the buffer(s) used to store the transmitted frame is released to the port-dedicated and/or common buffer pool(s).

Claims

1. A buffer management system for a network gateway, comprising:

a network interface in communication with at least one network, said interface providing P ports for receiving a data block from and transmitting said date block to said at least one network, wherein P is a positive, non-zero integer;

a buffer memory providing B buffers in communication with said network interface, each of said B buffers assigned to one of P+1 buffer pools, wherein B is an integer not less than P;

a control memory area in communication with said network interface;

a buffer and manager in communication with said network interface, said buffer memory, and said control memory area, said manager regulating storage and retrieval of said data block within at least one of said B buffers; and

a processor interface in communication with said network interface, said buffer memory, said control memory and said manager enabling manipulation of said data block by a processor after storage within said at least one buffer and before transmission of said data block from said network interface,

wherein P of said P+1 buffer pools are dedicated buffer pools, each assigned exclusively to a respective one of said P ports for storage of data blocks, or portions thereof, received at said respective port, and

wherein one of said P+1 buffer pools is a common buffer pool assigned to all of said P ports for storage of data blocks, or portions thereof, received at the respective port.

2. The system according to claim 1, wherein each of said B buffers in said buffer memory is divided into a first portion and a second portion.

3. The system according to claim 2, wherein said first and second portions each provide consecutive memory locations.

4. The system according to claim 2, wherein said first portion is disposed within a SRAM and said second portion is disposed within a DRAM.

5. The system according to claim 4, wherein said control memory is disposed within a SRAM.

6. The system according to claim 5, wherein said control memory and said first portion are disposed within one SRAM.

7. The system according to claim 1, wherein each of said P ports stores data blocks, or portions thereof, in said respective dedicated buffer pool until all of said buffers assigned to said dedicated buffer pool are used prior to storing data blocks, or portions thereof, in said common buffer pool.

8. A method of receiving and transmitting a data block in a network gateway having a buffer set addressed by buffer lists, the buffer set associated with a port set, the method comprising:

receiving said data block at a first port of said port set;

referring to a first buffer list having addresses of first buffers accessible only by said first port to retrieve addresses of unused first buffers by;

maintaining a first control block for said first buffer list in a memory access controller, said first control block containing a label corresponding to each of said first buffer addresses in said first buffer list, and

storing said first control block in a memory access controller register having multiple pointers associated with said first control block, said multiple pointers providing an indication of used first buffers and unused first buffers whose addresses are within said first buffer list;

referring to a second buffer list having addresses of second buffers accessible by every port in said port set to retrieve addresses of unused second buffers;

storing said data block in said unused first buffers, and in said second unused buffers after all of said unused first buffers have been used for storing; and

transmitting said data block at a second port of said gateway.

9. The method according to claim 8, wherein the step of receiving said data block further comprises:

correlating a receive port identifier with said first buffer list, said receive port identifier identifying said first port on which said data block was received.

10. The method according to claim 9, wherein the step of storing said data block further comprises adjusting said first control block multiple pointers to indicate usage of at least one first buffer addressed by said first buffer list.

11. The method according to claim 8, wherein the step of referring to a second buffer list further comprises:

maintaining a second control block for said second buffer list in a memory access controller, said second control block containing a label corresponding to each of said second buffer addresses in said second buffer list.

12. The method according to claim 11, wherein the step of referring to a second buffer list further comprises:

storing said second control block in a memory access controller register having multiple pointers associated with said second control block, said multiple pointers providing an indication of used second buffers and unused second buffers whose addresses are within said second buffer list.

13. The method according to claim 12, wherein the step of referring to a second buffer list further comprises:

maintaining a memory access controller register containing labels corresponding to reserved second buffers whose addresses are within said second buffer list, said reserved second buffers being inaccessible to said ports.

14. The method according to claim 12, wherein the step of storing said data block further comprises adjusting said second control block multiple pointers to indicate usage of at least one second buffer addressed by said second buffer list.

15. The method according to claim 8, wherein the step of storing said data block further comprises:

writing a first portion of said data block in a first memory device; and

writing a second portion of said data block in a second memory device.

16. The method according to claim 8, wherein the step of transmitting said data block further comprises:

indicating within said first buffer list that each first buffer address corresponding to a first buffer in which said data block was stored is now unused; and

indicating within said second buffer list that each second buffer address corresponding to a second buffer in which said data block was stored, if any, is now unused.

17. A method of receiving and transmitting a data block in a network gateway having a buffer set addressed by buffer lists, the buffer set associated with a port set, the method comprising:

receiving said data block at a first port of said port set;

referring to a first buffer list having addresses of first buffers accessible only by said first port to retrieve addresses of unused first buffers;

referring to a second buffer list having addresses of second buffers accessible by every port in said port set to retrieve addresses of unused second buffers by;

maintaining a second control block for said second buffer list in a memory access controller, said second control block containing a label corresponding to each of said second buffer addresses in said second buffer list, and

storing said second control block in a memory access controller register having multiple pointers associated with said second control block, said multiple pointers providing an indication of used second buffers and unused second buffers whose addresses are within said second buffer list;

storing said data block in said unused first buffers, and in said second unused buffers after all of said unused first buffers have been used for storing; and

transmitting said data block at a second port of said gateway.

18. The method according to claim 17, wherein the step of receiving said data block further comprises:

correlating a receive port identifier with said first buffer list, said receive port identifier identifying said first port on which said data block was received.

19. The method according to claim 17, wherein the step of referring to a first buffer list further comprises:

maintaining a first control block for said first buffer list in a memory access controller, said first control block containing a label corresponding to each of said first buffer addresses in said first buffer list.

20. The method according to claim 19, wherein the step of referring to a first buffer list further comprises:

storing said first control block in a memory access controller register having multiple pointers associated with said first control block, said multiple pointers providing an indication of used first buffers and unused first buffers whose addresses are within said first buffer list.

21. The method according to claim 20, wherein the step of storing said data block further comprises adjusting said first control block multiple pointers to indicate usage of at least one first buffer addressed by said first buffer list.

22. The method according to claim 17, wherein the step of referring to a second buffer list further comprises:

maintaining a memory access controller register containing labels corresponding to reserved second buffers whose addresses are within said second buffer list, said reserved second buffers being inaccessible to said ports.

23. The method according to claim 17, wherein the step of storing said data block further comprises adjusting said second control block multiple pointers to indicate usage of at least one second buffer addressed by said second buffer list.

24. The method according to claim 17, wherein the step of storing said data block further comprises:

writing a first portion of said data block in a first memory device; and

writing a second portion of said data block in a second memory device.

25. The method according to claim 17, wherein the step of transmitting said data block further comprises:

indicating within said first buffer list that each first buffer address corresponding to a first buffer in which said data block was stored is now unused; and

indicating within said second buffer list that each second buffer address corresponding to a second buffer in which said data block was stored, if any, is now unused.