Support structures for an intelligent low power serial bus

• US 5,812,796 A
• Filed: 08/18/1995
• Issued: 09/22/1998
• Est. Priority Date: 08/18/1995
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: General Magic, Inc.
• Inventors: Fadell, Anthony M., Broedner, Walter F.
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/517,003
• Time in Patent Office: 1,131 Days
• Field of Search: 395/750, 395/733, 395/306, 395/309, 395/283, 395/284, 395/285, 395/835, 395/839, 364/707
• US Class Current: 710/302
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. Each peripheral device includes a plurality of serial bus support structures. For example, the serial bus support structures can include an interrupt generation circuit, a power-on circuit, and a wake-up interrupt generation circuit, and a wake-up interrupt propagation circuit.

Claims

1. In a peripheral device, a serial bus support circuit comprising:

a power supply line;

a downstream interrupt line coupled to said power supply line wherein upon connection of a downstream peripheral device to said downstream interrupt line, said downstream interrupt line has a first level, and upon disconnection of said downstream peripheral device from said downstream interrupt line, said downstream interrupt line has a second level;

an upstream interrupt line; and

a bus interface circuit having a downstream interrupt in terminal coupled to said downstream interrupt line, and an upstream interrupt out terminal coupled to said upstream interrupt line wherein said bus interface circuit passes a signal on said downstream interrupt in terminal to said upstream interrupt out terminal so that upon said downstream peripheral device being disconnected from said downstream interrupt line, said second level on said downstream interrupt line is propagated to said upstream interrupt line so as to automatically generate an interrupt by said serial bus support circuit upon disconnection of said downstream peripheral device from said peripheral device.

2. In a peripheral device, a serial bus support circuit as in claim 1 further comprising a resistive element having a first lead connected to said power supply line, and a second lead connected to said downstream interrupt line so as to couple said downstream interrupt line to said power supply line.

3. In a peripheral device, a serial bus support circuit as in claim 2 wherein said resistive element is a resistor.

4. In a peripheral device, a serial bus support circuit as in claim 1 further comprising a first inverter having an input terminal connected to said downstream interrupt line;

a line connected to said power supply line; and

an output terminal.

5. In a peripheral device, a serial bus support circuit as in claim 4 further comprising a second inverter having an input terminal connected to said output terminal of said first inverter;

a line connected to said power supply line; and

an output terminal connected to said downstream interrupt in terminal of said bus interface circuit.

6. In a peripheral device, a serial bus support circuit as in claim 5 further comprising a third inverter having an input terminal connected to said upstream interrupt out terminal of said bus interface circuit;

a line connected to said power supply line; and

an output terminal.

7. In a peripheral device, a serial bus support circuit as in claim 6 further comprising a fourth inverter having an input terminal connected to said output terminal of said third inverter;

a line coupled to said power supply line; and

an output terminal connected to said upstream interrupt line.

8. In a peripheral device, a serial bus support circuit as in claim 7 wherein said fourth inverter comprises a discrete inverter.

9. In a peripheral device, a serial bus support circuit as in claim 1 further comprising:

a wake-up interrupt propagation circuit having an input line connected to said downstream interrupt line; and

an output line connected to said upstream interrupt line.

10. In a peripheral device, a serial bus support circuit as in claim 9 wherein said wake-up interrupt propagation circuit further comprises:

a first gate having a first input terminal connected to said input line of said wake-up interrupt propagation circuit;

a second input terminal connected to said power supply line, and an output terminal connected to said output line of said wake-up interrupt propagation circuit;

wherein upon a voltage on said power supply line having a first state, said first gate passes a signal on said downstream interrupt line through said first gate to said upstream interrupt line and so bypasses said bus interface circuit; and

upon said voltage on said power supply line having a second state, said first gate blocks passage of said signal on said downstream interrupt line through said gate to said upstream interrupt line.

11. In a peripheral device, a serial bus support circuit as in claim 10 wherein said first gate comprises a transistor having a first lead connected to said first input terminal of said first gate;

a second lead coupled to said second input terminal of said first gate; and

a third lead connected to said output terminal of said first gate.

12. In a peripheral device, a serial bus support circuit as in claim 11 wherein said transistor comprises a PNP transistor having an emitter connected to said first lead;

a base connected to said second lead; and

a collector connected to said third lead.

13. In a peripheral device, a serial bus support circuit as or claim 9 further comprising:

a wake-up interrupt generation circuit having an output line connected to said upstream interrupt line.

14. In a peripheral device, a serial bus support circuit as in claim 13 wherein said wake-up interrupt generation circuit further comprises:

a microcontroller having a wake-up interrupt generation terminal;

a second gate having a first input terminal coupled to said wake-up interrupt generation terminal;

a second input terminal connected to said power supply line; and

an output terminal coupled to said output line of said wake-up interrupt generation circuit;

wherein upon a voltage on said power supply line having a first state, said second gate passes a signal from said wake-up interrupt generation terminal through said second gate to said upstream interrupt line; and

upon said voltage on said power supply line having a second state, said second gate blocks passage of said signal from said wake-up interrupt generation terminal through said second gate to said upstream interrupt line.

15. In a peripheral device, a serial bus support circuit as in claim 14 wherein said second gate comprises a second transistor having a first lead connected to said first input terminal of said second gate;

a second lead coupled to said second input terminal of said second gate; and

a third lead connected to said third terminal of said second gate.

16. In a peripheral device, a serial bus support circuit as in claim 15 wherein said second transistor comprises a second PNP transistor having an emitter connected to said first lead;

a base connected to said second lead; and

a collector connected to said third lead.

17. In a peripheral device, a serial bus support circuit as in claim 14 wherein said wake-up interrupt generation circuit further comprises:

a peripheral device power supply line;

a first resistive element having a first terminal connected to said peripheral device power supply line; and

a second terminal connected to said wake-up interrupt generation terminal; and

a second transistor having a first lead connected to said peripheral device power supply line;

a second lead coupled to said wake-up interrupt generation terminal; and

a third lead connected to said first input terminal of said second gate.

18. In a peripheral device, a serial bus support circuit as in claim 17 wherein said wake-up interrupt generation circuit further comprises:

a second resistive element having a first terminal connected to said wake-up interrupt generation terminal; and

a second terminal connected to second lead of said second transistor.

19. In a peripheral device, a serial bus support circuit as in claim 17 wherein said second transistor comprises a NPN transistor having an emitter connected to said first lead;

a base connected to said second lead; and

a collector connected to said third lead.

20. In a peripheral device, a serial bus support circuit as in claim 14 wherein said wake-up interrupt generation circuit further comprises a diode having an anode connected to said output terminal of said second gate;

and a cathode connected to said output line of said wake-up interrupt generation circuit.

21. In a peripheral device, a serial bus support circuit as in claim 13 wherein said bus interface circuit further comprising:

a peripheral power on terminal;

a standby power supply line;

a switch having a first terminal coupled to said standby power supply line;

a second terminal coupled to a reference voltage, and a third terminal coupled to said peripheral power on terminal wherein

upon a first voltage being applied to said peripheral power on terminal by said bus interface circuit, said first switch terminal is connected to second switch terminal by said first voltage on said third terminal; and

otherwise said first switch terminal and said second switch terminal are disconnected;

an inverter having an input terminal connected to said first switch terminal and an output terminal connected to a power supply line for said peripheral device.

22. In a peripheral device, a serial bus support circuit as in claim 21 wherein said switch comprises a transistor having a first lead connected to said first switch terminal;

a second lead connected to said second switch terminal; and

a third lead connected to said third switch terminal.

23. In a peripheral device, a serial bus support circuit as in claim 22 wherein said transistor comprises a field effect transistor having a gate wherein said gate is connected to said third lead.

24. In a peripheral device, a serial bus support circuit as in claim 1 further comprising a first inverter having an input terminal connected to said upstream interrupt out terminal of said bus interface circuit;

a line connected to said power supply line; and

an output terminal.

25. In a peripheral device, a serial bus support circuit as in claim 24 further comprising a second inverter having an input terminal connected to said output terminal of said first inverter;

a line coupled to said power supply line; and

an output terminal connected to said upstream interrupt line.

26. In a peripheral device, a serial bus support circuit as in claim 1 further comprising:

a wake-up interrupt generation circuit having an output line connected to said upstream interrupt line.

27. In a peripheral device, a serial bus support circuit as in claim 26 wherein said wake-up interrupt generation circuit further comprises:

a microcontroller having a wake-up interrupt generation terminal;

a first gate having a first input terminal coupled to said wake-up interrupt generation terminal;

a second input terminal connected to said power supply line; and

an output terminal coupled to said output line of said wake-up interrupt generation circuit;

wherein upon a voltage on said power supply line having a first state, said first gate passes a signal from said wake-up interrupt generation terminal through said first gate to said upstream interrupt line; and

upon said voltage on said power supply line having a second state, said first gate blocks passage of said signal from said wake-up interrupt generation terminal through said second gate to said upstream interrupt line.

28. In a peripheral device, a serial bus support circuit as in claim 27 wherein said first gate comprises a transistor having a first lead connected to said first input terminal of said first gate;

a second lead coupled to said second input terminal of said first gate; and

a third lead connected to said third terminal of said first gate.

29. In a peripheral device, a serial bus support circuit as in claim 28 wherein said transistor comprises a first PNP transistor having an emitter connected to said first lead;

a base connected to said second lead; and

a collector connected to said third lead.

30. In a peripheral device, a serial bus support circuit as in claim 27 wherein said wake-up interrupt generation circuit further comprises:

a peripheral device power supply line;

a first resistive element having a first terminal connected to said peripheral device power supply line; and

a second terminal connected to said wake-up interrupt generation terminal; and

a transistor having a first lead connected to said peripheral device power supply line;

a second lead coupled to said wake-up interrupt generation terminal; and

a third lead connected to said first input terminal of said first gate.

31. In a peripheral device, a serial bus support circuit as in claim 30 wherein said wake-up interrupt generation circuit further comprises:

a second resistive element having a first terminal connected to said wake-up interrupt generation terminal; and

a second terminal connected to second lead of said transistor.

32. In a peripheral device, a serial bus support circuit as in claim 30 wherein said transistor comprises a NPN transistor having an emitter connected to said first lead;

a base connected to said second lead; and

a collector connected to said third lead.

33. In a peripheral device, a serial bus support circuit as in claim 27 wherein said wake-up interrupt generation circuit further comprises a diode having an anode connected to said output terminal of said first gate;

and a cathode connected to said output line of said wake-up interrupt generation circuit.

34. In a peripheral device, a serial bus support circuit as in claim 26 wherein said bus interface circuit further comprising:

a peripheral power on terminal;

a standby power supply line;

a switch having a first terminal coupled to said standby power supply line;

a second terminal coupled to a reference voltage, and a third terminal coupled to said peripheral power on terminal wherein

upon a first voltage being applied to said peripheral power on terminal by said bus interface circuit, said first switch terminal is connected to second switch terminal by said first voltage on said third terminal; and

otherwise said first switch terminal and said second switch terminal are disconnected;

an inverter having an input terminal connected to said first switch terminal and an output terminal connected to a power supply line for said peripheral device.

35. In a peripheral device, a serial bus support circuit as in claim 34 wherein said switch comprises a transistor having a first lead connected to said first switch terminal;

a second lead connected to said second switch terminal; and

a third lead connected to said third switch terminal.

36. In a peripheral device, a serial bus support circuit as in claim 35 wherein said transistor comprises a field effect transistor having a gate wherein said gate is connected to said third lead.

37. In a peripheral device, a serial bus support circuit comprising:

a power supply line;

a downstream interrupt line;

a pull-up resistive element connected to said downstream interrupt line;

a first inverter having an input terminal connected to said downstream interrupt line; and

an output terminal;

a second inverter having an input terminal connected to said output terminal of said first inverter; and

an output terminal;

a bus interface circuit having a downstream interrupt in terminal connected to output terminal of said second inverter; and

an upstream interrupt out terminal;

a third inverter having an input terminal connected to said upstream interrupt out terminal;

and an output terminal;

a fourth inverter having an input terminal connected to said output terminal of said third inverter; and

an output terminal;

an upstream interrupt line connected to said output terminal of said fourth inverter;

a wake-up interrupt propagation circuit having an input line connected to said downstream interrupt line; and

an output line connected to said upstream interrupt line; and

a wake-up interrupt generation circuit having an output line connected to said upstream interrupt line.

38. In a peripheral device, a wake-up interrupt propagation structure comprising:

a power supply line;

a downstream interrupt line;

an upstream interrupt line;

a bus interface circuit having a downstream interrupt in terminal coupled to said downstream interrupt line; and

an upstream interrupt out terminal coupled to said upstream interrupt line wherein said bus interface circuit passes a signal on said downstream interrupt in terminal to said upstream interrupt out terminal; and

a gate having a first input terminal connected to said downstream interrupt line;

a second input terminal connected to said power supply line; and

an output terminal connected to said upstream interrupt line

wherein upon a voltage on said power supply line having a first state, said gate passes a signal on said downstream interrupt line through said gate to said upstream interrupt line and so bypasses said bus interface circuit; and

upon said voltage on said power supply line having a second state, said gate blocks passage of said signal on said downstream interrupt line through said gate to said upstream interrupt line.

39. In a peripheral device, a wake-up interrupt propagation structure as in claim 38 wherein said gate comprises a transistor having a first lead connected to said first input terminal of said gate;

a second lead coupled to said second input terminal of said gate; and

a third lead connected to said output terminal of said gate.

40. In a peripheral device, a wake-up interrupt propagation structure as in claim 39 wherein said transistor comprises a PNP transistor having an emitter connected to said first lead;

a base connected to said second lead; and

a collector connected to said third lead.

41. In a peripheral device, a wake-up interrupt generation structure comprising:

a power supply line;

a downstream interrupt line;

an upstream interrupt line;

a bus interface circuit having a downstream interrupt in terminal coupled to said downstream interrupt line; and

an upstream interrupt out terminal coupled to said upstream interrupt line wherein said bus interface circuit passes a signal on said downstream interrupt in terminal to said upstream interrupt out terminal; and

a microcontroller having a wake-up interrupt generation terminal;

a gate having a first input terminal coupled to said wake-up interrupt generation terminal;

a second input terminal connected to said power supply line; and

an output line coupled to said upstream interrupt line;

wherein upon a voltage on said power supply line having a first state, said gate passes a signal from said wake-up interrupt generation terminal through said gate to said upstream interrupt line; and

upon said voltage on said power supply line having a second state, said gate blocks passage of said signal from said wake-up interrupt generation terminal through said gate to said upstream interrupt line.

42. In a peripheral device, a wake-up interrupt generation structure as in claim 41 wherein said gate comprises a first transistor having a first lead connected to said first input terminal of said gate;

a second lead coupled to said second input terminal of said gate; and

a third lead connected to said output terminal of said gate.

43. In a peripheral device, a wake-up interrupt generation structure as in claim 42 wherein said first transistor comprises a PNP transistor having an emitter connected to said first lead;

a base connected to said second lead; and

a collector connected to said third lead.

44. In a peripheral device, a wake-up interrupt generation structure as in claim 41 wherein said wake-up interrupt generation structure further comprises:

a peripheral device power supply line;

a first resistive element having a first terminal connected to said peripheral device power supply line; and

a second terminal connected to said wake-up interrupt generation terminal; and

a transistor having a first lead connected to said peripheral device power supply line;

a second lead coupled to said wake-up interrupt generation terminal; and

a third lead connected to said first input terminal of said gate.

45. In a peripheral device, a wake-up interrupt generation structure as in claim 44 wherein said wake-up interrupt generation structure further comprises:

a second resistive element having a first terminal connected to said wake-up interrupt generation terminal; and

a second terminal connected to second lead of said transistor.

46. In a peripheral device, a wake-up interrupt generation structure as in claim 45 wherein said transistor comprises a NPN transistor having an emitter connected to said first lead;

a base connected to said second lead; and

a collector connected to said third lead.

47. In a peripheral device, a wake-up interrupt generation structure as in claim 46 wherein said wake-up interrupt generation structure further comprises a diode having an anode connected to said output terminal of said gate;

and a cathode connected to said output line of said wake-up interrupt generation structure.

48. In a peripheral device, a power on circuit comprising:

a bus interface circuit having a peripheral power on terminal;

a standby power supply line;

a switch having a first terminal coupled to said standby power supply line;

a second terminal coupled to a reference voltage, and a third terminal coupled to said peripheral power on terminal wherein

upon a first voltage being applied to said peripheral power on terminal by said bus interface circuit, said first switch terminal is connected to second switch terminal by said first voltage on said third terminal; and

otherwise said first switch terminal and said second switch terminal are disconnected;

an inverter having an input terminal connected to said first switch terminal; and

an output terminal connected to a power supply line for said peripheral device.

49. In a peripheral device, a power on circuit as in claim 48 wherein said switch comprises a transistor having a first lead connected to said first switch terminal;

a second lead connected to said second switch terminal and a third lead connected to said third switch terminal.

50. In a peripheral device, a power on circuit as in claim 49 wherein said transistor comprises a field effect transistor having a gate wherein said gate is connected to said third lead.

51. A method for powering up a peripheral device on a serial bus comprising:

connecting a terminal of a bus interface circuit to a power supply circuit of said peripheral device wherein upon application of a first voltage level on said terminal said power supply circuit is off and upon application of a second voltage level on said terminal said power supply circuit is on;

coupling said bus interface circuit to said serial bus; and

issuing a power-on command over said serial bus to said bus interface circuit wherein in response to said power-on command, said bus interface circuit generates said second voltage level on said terminal.