Enhanced cardbus adapter and associated buffering circuitry for interfacing multiple cardbus/16 bit PC cards

• US 5,812,827 A
• Filed: 03/10/1997
• Issued: 09/22/1998
• Est. Priority Date: 01/30/1995
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: McGrath, H. John
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): MOHAMED, AYNI Y
• Application Number:
  US08/812,913
• Time in Patent Office: 561 Days
• Field of Search: 395/500, 395/309
• US Class Current: 703/25
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence

Abstract

An otherwise conventional CardBus adapter is provided with an additional status register, a small number of additional pins, and associated external buffering circuitry. Furthermore, a number of the CardBus adapter'"'"'s existing pins are either eliminated, redefined or used for multiple purposes. As a result, the CardBus adapter in conjunction with the associated external buffering circuitry is able to interface to multiple CardBus/16-bit PC Cards at the same time.

Claims

1. An enhanced CardBus adapter comprising:

a) a single status pin for receiving a consolidated status change control signal that, when set, denotes a status change for one of a plurality of interfacing PCMCIA cards;

b) a status control pin for outputting a status enabling signal for enabling reading of externally buffered individual card presence and status change control signals of the plurality of interfacing PCMCIA cards;

c) a plurality of address/data pins for transfer addresses/data to and from the plurality of interfacing PCMCIA cards, wherein some of the address/data pins are selectively used for receiving the externally buffered individual card presence and status change control signals of the plurality of interfacing PCMCIA cards;

d) multiple sets of transactional pins, one set for each interfacing PCMCIA card, for correspondingly exchanging transactional signals with the interfacing PCMCIA cards through a plurality of external drivers; and

e) a status register, coupled to the address/data pins that are also used for receiving the externally buffered individual card presence and status change control signals of the interfacing PCMCIA cards being read, for storing the received individual card presence and status change control signals of the intefacing PCMCIA cards.

2. The enhanced CardBus adapter as set forth in claim 1, wherein the enhanced CardBus adapter further comprises:

f) multiple pairs of address/data control pins for outputting address/data control signals for controlling selective transfers of address/data signals to and from one of the interfacing PCMCIA cards.

3. The enhanced CardBus adapter as set forth in claim 1, wherein the enhanced CardBus adapter further comprises:

d) multiple sets of transactional pins, one set for each interfacing PCMCIA card, for correspondingly exchanging transactional signals with the interfacing PCMCIA cards.

4. The enhanced CardBus adapter as set forth in claim 1, wherein the enhanced CardBus adapter further comprises:

d) multiple pairs of address/data control pins for outputting address/data control signals for controlling selective transfers of address/data signals to and from one of the interfacing PCMCIA cards.

5. An apparatus for interfacing multiple PCMCIA cards at the same time, the apparatus comprising:

a) an enhanced CardBus adapter having

a.1) a single status pin for receiving a consolidated status change control signal that, when set, denotes status change for one of a plurality of interfacing PCMCIA cards,

a.2) a status control pin for outputting a status enabling signal for enabling reading of externally buffered individual card presence and status change control signals of the plurality of interfacing PCMCIA cards,

a.3) a plurality of address/data pins for transferring addresses/data to and from the plurality of interfacing PCMCIA cards, wherein some of the address/data pins are also used for receiving the externally buffered individual card presence and status change control signals of the plurality of interfacing PCMCIA cards being read; and

b) associated buffering circuitry for the enhanced CardBus adapter including

b.1) a PLD for generating the consolidated status change signal responsive to the individual card presence and status change control signals of the plurality of interfacing PCMCIA cards, and

b.2) a first plurality of buffers for buffering and providing the individual card presence and status change control signals of the plurality of interfacing PCMCIA cards responsive to the status enabling signal.

6. The apparatus as set forth in claim 5, wherein,

the enhanced CardBus adapter also has

a.4) a status register coupled to the address/data pins that are also used for receiving the externally buffered individual card presence and status change control signals of the interfacing PCMCIA cards being read, for storing the received individual card presence and status change control signals of the interfacing PCMCIA cards.

7. The apparatus as set forth in claim 5, wherein,

the enhanced CardBus adapter also has

a.4) multiple sets of transactional pins, one set for each interfacing PCMCIA card, for correspondingly exchanging transactional signals with the interfacing PCMCIA cards.

8. The apparatus as set forth in claim 7, wherein,

the associated buffering circuitry further includes

b.3) a plurality of drivers for electrically driving the transactional signals to and from the interfacing PCMCIA cards.

9. The apparatus as set forth in claim 5, wherein,

the enhanced CardBus adapter also has

a.4) multiple pairs of address/data control pins for outputting address/data control signals for controlling selective transfers of address/data signals to and from one of the interfacing PCMCIA cards;

and

the associated buffering circuitry further includes

b.3) a second plurality of buffers for buffering the address/data signals of the interfacing PCMCIA cards.

10. The apparatus as set forth in claim 9, wherein,

the second plurality of buffers comprise a first group of buffers organized into multiple sets for correspondingly buffering a first subset of the address/data signals of the various interfacing PCMCIA cards, and a second group of buffers organized as a single set for buffering a second subset of the address/data signals of all interfacing PCMCIA cards.

11. A method for simultaneously interfacing a plurality of PCMCIA cards to a single CardBus adapter at the same time, the method comprising the steps of:

a) externally generating a consolidated status change control signal for the CardBus adapter to denote status change for one of the plurality of interfacing PCMCIA cards;

b) externally buffering individual card presence and status change control signals of the plurality of interfacing PCMCIA cards;

c) generating a status enabling signal by the CardBus adapter to enable reading of the buffered individual card presence and status change control signals of the plurality of interfacing PCMCIA cards; and

d) reading the buffered individual card presence and status change control signals of the plurality of interfacing PCMCIA cards by the CardBus adapter through a subset of a plurality of address/data pins of the CardBus adapter normally used for transferring addresses/data to and from the plurality of interfacing PCMCIA cards; and

e) exchanging transaction signals with the interfacing PCMCIA cards using multiple sets of corresponding transactional pins disposed on the CardBus adapter with external drivers.

12. The method as set forth in claim 11, wherein the method further comprises the step of:

e) receiving and storing the individual card presence and status change control signals of the interfacing PCMCIA cards by the CardBus adapter in a status register of the CardBus adapter.

13. The method as set forth in claim 11, wherein step (e) further comprises driving the transactional signals to and from the interfacing PCMCIA cards with a plurality of drivers external to the CardBus adapter.

14. The method as set forth in claim 11, wherein the method further comprises:

e) externally buffering address/data signals being transferred to and from the interfacing PCMCIA cards; and

f) generating address/data control signals for controlling selective transfers of address/data signals to and from one of the interfacing PCMCIA cards through the address/data pins of the CardBus adapter.

15. A motherboard of a computer system, the motherboard comprising

a) an I/O bus for transferring I/O signals;

b) an enhanced CardBus adapter, coupled to the I/O bus, the enhanced CardBus adapter comprising;

b.1) a status pin for receiving a consolidated status change control signal that, when set, denotes status change for one of a plurality of interfacing PCMCIA cards,

b.2) a status control pin for outputting a status enabling signal for enabling reading of externally buffered individual card presence and status change control signals of the plurality of interfacing PCMCIA cards,

b.3) a plurality of address/data pins for transferring addresses/data to and from the plurality of interfacing PCMCIA cards, wherein some of the address/data pins are also used for receiving the externally buffered individual card presence and status change control signals of the plurality of interfacing PCMCIA cards being read;

c) associated buffering circuitry for the enhanced CardBus adapter including

c.1) a programmable logic device (PLD) for generating the consolidated status change signal responsive to the individual card presence and status change control signals of the plurality of interfacing PCMCIA cards,

c.2) a first plurality of buffers for buffering and providing the individual card presence and status chance control signals of the plurality of interfacing PCMCIA cards responsive to the status enabling signal; and

d) a plurality of connectors coupled to the buffering circuitry for removably receiving the plurality of interfacing PCMCIA cards.

16. The motherboard as set forth in claim 15, wherein,

the enhanced CardBus adapter also has

b.4) a status register coupled to the address/data pins that are also used for receiving the externally buffered individual card presence and status change control signals of the interfacing PCMCIA cards being read, for storing the received individual card presence and status change control signals of the interfacing PCMCIA cards.

17. The motherboard as set forth in claim 15, wherein,

the enhanced CardBus adapter also has

b.4) multiple sets of transactional pins, one set for each interfacing PCMCIA card, for correspondingly exchanging transactional signals with the interfacing PCMCIA cards.

18. The motherboard as set forth in claim 17, wherein,

the associated buffering circuitry further includes

c.3) a plurality of drivers for electrically driving the transactional signals to and from the interfacing PCMCIA cards.

19. The motherboard as set forth in claim 18, wherein,

the enhanced CardBus adapter also has

b.4) multiple pairs of address/data control pins for outputting address/data control signals for controlling selective transfers of address/data signals to and from one of the interfacing PCMCIA cards;

and

the associated buffering circuitry further includes

c.3) a second plurality of buffers for buffering the address/data signals of the interfacing PCMCIA cards.

20. A computer system comprising:

a) a processor for executing instructions;

b) a memory subsystem coupled to the processor for storing the instructions and data; and

c) an I/O subsystem coupled to the processor and memory subsystem including

c.1) an enhanced CardBus adapter having

c.1.1) a status pin for receiving a consolidated status change control signal, when set, denoting status change for one of a plurality interfacing PCMCIA cards,

c.1.2) a status control pin for providing a status enabling signal for enabling reading of externally buffered individual card presence and status change control signals of the interfacing PCMCIA cards,

c.1.3) a plurality of address/data pins for transferring addresses/data to and from the interfacing PCMCIA cards, wherein some of the address/data pins are also used for receiving the externally buffered individual card presence and status change control signals of the interfacing PCMCIA cards being read;

c.2) associated buffering circuitry for the enhanced CardBus adapter including

c.2.1) a PLD for generating the consolidated status change signal responsive to the individual card presence and status change control signals of the interfacing PCMCIA cards,

c.2.2) a first plurality of buffers for buffering and providing the individual card presence and status change control signals of the interfacing PCMCIA cards responsive to the status enabling signal;

c.3) a plurality of connectors coupled to the buffering circuitry for removably receiving the PCMCIA cards.

21. The computer system as set forth in claim 20, wherein,

the enhanced CardBus adapter also has

c.1.4) a status register coupled to the address/data pins that are also used for receiving the externally buffered individual card presence and status change control signals of the interfacing PCMCIA cards being read, for storing the received individual card presence and status change control signals of the interfacing PCMCIA cards.

22. The computer system as set forth in claim 20, wherein,

the enhanced CardBus adapter also has

c.1.4) multiple sets of transactional pins, one set for each interfacing PCMCIA card, for correspondingly exchanging transactional signals with the interfacing PCMCIA cards.

23. The computer system as set forth in claim 22, wherein,

the associated buffering circuitry further includes

c.2.3) a plurality of drivers for electrically driving the transactional signals to and from the interfacing PCMCIA cards.

24. The computer system as set forth in claim 20, wherein,

the enhanced CardBus adapter also has

c.1.4) multiple pairs of address/data control pins for outputting address/data control signals for controlling selective transfers of address/data signals to and from one of the interfacing PCMCIA cards;

and

the associated buffering circuitry further includes

c.2.3) a second plurality of buffers for buffering the address/data signals of the interfacing PCMCIA cards.