Method and apparatus providing multiple voltages and frequencies selectable based on real time criteria to control power consumption

• US 5,812,860 A
• Filed: 02/12/1996
• Issued: 09/22/1998
• Est. Priority Date: 02/12/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Smith, Lionel S., Horden, A. Ira, Gorman, Steven D.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): DHARIA, RUPAL
• Application Number:
  US08/599,648
• Time in Patent Office: 953 Days
• Field of Search: 395/750, 395/556, 395/750.04, 395/750.07, 327/113, 327/544, 364/707, 326/80, 326/81, 331/143
• US Class Current: 713/322
• CPC Class Codes: G06F 1/3203 Power management, i.e. event-based initiation of a power-saving mode
• CPC Class Codes: G06F 1/324 by lowering clock frequency
• CPC Class Codes: G06F 1/3296 by lowering the supply or operating voltage
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A method and system for reducing power consumption in a processor core. A state machine is used to coordinate a frequency from a clock signal generator with a voltage from a voltage regulator which is sufficient to allow operation of the processor at that frequency. Both the clock signal generator and the voltage regulator must be able to generate at least two frequencies or voltages, respectively. A level of processor need is tracked and the lowest frequency/voltage pair that will allow the processor core to satisfy the need is selected. The level of processor need is monitored either periodically or continually such that a new frequency/voltage pair can be dynamically selected as the application mix changes.

Claims

1. A system comprising:

a processor coupled to a memory by a bus, the processor having a processor core and a pad ring, the processor core having an independent power supply;

a voltage regulator providing a plurality of voltages and providing the independent power supply;

a clock signal generator providing a clock signal at a plurality of frequencies;

a state machine to coordinate voltage and clock frequency to the processor core; and

an operating system running on the processor, the operating system monitoring an application mix executing in the processor to determine a required frequency, and determining a minimum voltage at which the processor core can operate at the required frequency, wherein the operating system directs the state machine to enter a state in which the required frequency is supplied by the clock signal generator and a closest supported voltage equal to or greater than the minimum voltage is supplied by the voltage regulator.

2. The system of claim 1 wherein the voltage regulator provides one of an idle voltage or a peak voltage.

3. The system of claim 1 wherein the voltage regulator can provide one voltage corresponding to each frequency supported by the clock signal generator.

4. A method of reducing power consumption by a processor core and a pad ring comprising the steps of:

accepting a measure of processor core performance need of each application currently seeking access to the processor core;

accumulating each measure of processor core performance need to find total current need;

calculating a minimum frequency that will allow the processor core to meet the total current need for the time period;

selecting a lowest supported frequency equal to or greater than the minimum frequency to be a required frequency;

finding a minimum supported voltage at which the processor core can operate at the required frequency independent of a voltage required by the pad ring;

supplying the required frequency and the minimum supported voltage to the processor core; and

dynamically changing the required frequency and the minimum supported voltage supplied responsive to a change in the current application mix.

5. A method of reducing power consumption by a processor core and a pad ring comprising the steps of:

establishing a maximum allowable power consumption;

finding a maximum supported frequency which will allow the processor core to remain below the maximum allowable power consumption at the minimum supported voltage;

selecting a required frequency to be less than or equal to the maximum supported frequency;

finding a minimum supported voltage at which the processor core can operate at the required frequency independent of a voltage required by the pad ring;

supplying the required frequency and the minimum supported voltage to the processor core; and

dynamically changing the required frequency and the minimum supported voltage supplied responsive to a change in the current application mix.

6. The method of claim 5 wherein a required frequency less than the maximum supported frequency is selected whenever a total processor core performance need of the current application mix can be met by a lower supported frequency.