Handshake minimizing serial to parallel bus interface in a data processing system

• US 5,812,881 A
• Filed: 04/10/1997
• Issued: 09/22/1998
• Est. Priority Date: 04/10/1997
• Status: Expired due to Term

• Current Assignee: MediaTek, Inc.
• Original Assignee: International Business Machines Corporation
• Inventors: Nguyen, Thang Q., Ku, Yi-Ming
• Primary Examiner(s): Kim, Kenneth S.
• Application Number:
  US08/827,744
• Time in Patent Office: 530 Days
• Field of Search: 395/891, 395/822, 395/800.38, 395/872
• US Class Current: 710/71
• CPC Class Codes: G06F 13/4045 where the bus bridge performs an extender function

Abstract

A serial/parallel interface for interfacing the serial port of a microcontroller with parallel bus devices, and a protocol for communicating with the same. The interface operates to maximize through-put with minimum handshaking. When the bus device is a nonvolatile memory containing the operating software of the microcontroller system, the interface provides for dynamic updating of the operating program. It also relieves the constraints imposed on the number of bus devices accessible to the microcontroller system because of the limited number of I/O pins available on the microcontroller.

Claims

1. A microcontroller system comprising:

a microcontroller having at least one parallel input/output ("I/O") bus, and a serial data port;

a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with said serial data port of said microcontroller, wherein a first data value communicated on said serial date port of said microcontroller is presented as a parallel data value on said parallel data bus, said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit; and

a bus device adaptable for receiving said address on said parallel address bus of said serial-to-parallel interface logic circuit, said bus device adapted for accessing said data bus to communicate said parallel data value,

wherein said serial-to-parallel interface logic circuit further comprises;

a shift resister for receiving serial data value, said shift register having a parallel output bus;

a clock sequencing logic circuit coupled to said microcontroller to recieve a serial clock signal, said clock sequencing logic providing a first clock signal for clocking said shift register;

an output data buffer for receiving a second data value on said parallel data bus of said-to-parallel interface logic circuit, said output data buffer operable for latching said data value on receipt of said first clock signal from said clock sequencing logic, said output data buffer asserting said second data value on said serial data port of said serial-to-parallel interface logic circuit;

an address logic circuit operable for receiving an address data value from said parallel bus of said shift register, said address data value capable of initializing a counter;

a control logic circuit operable for receiving a command value from said parallel output bus of said shift register, wherein said control logic circuitry configures said serial-to-parallel interface logic circuit to reflect an operation to be performed; and

an input data buffer for receiving a download data value from said parallel output bus of said shift register, said input data buffer providing said download data value on said parallel data bus on said serial-to-parallel interface logic circuit, wherein said input data value is operable for latching said download data value, and

wherein said control logic circuitry further comprise;

command logic circuitry adaptable for receiving said command value, and for providing a first command signal;

a read/write state machine adaptable for controlling read/write operations of said serial-to-parallel interface logic circuit in response to the first command signal received from said command logic circuitry; and

a row, column-count state machine for outputting a plurality of row/column register select signals, said plurality of row/column register select signals generated in response to a plurality of clock signals from said clock sequencing logic, wherein said address logic circuit includes a plurality of address registers adaptable for selection in response to said plurality of row/column select signals, and said input data buffer is adaptable for selection in response to said plurality of row/column select signals.

2. The microcontroller system of claim 1 wherein said plurality of address registers further comprise a plurality of multiplexers-with-latch.

3. A microcontroller system comprising:

a microcontroller having at least one parallel input/output ("I/O") bus, and a serial data port;

a serial-to-parallel interface logic circuit having a serial data port, a parallel address bus, and a parallel data bus, said serial data port adapted for communicating with said serial data port of said microcontroller, wherein a first data value communicated on said serial data port of said microcontroller is presented as a parallel data value on said parallel data bus said serial-to-parallel interface logic circuit providing an address on said parallel address bus of said serial-to-parallel interface logic circuit; and

a bus device adaptable for receiving said address on said parallel address bus of said serial-to-parallel interface logic circuit, said bus device adapted for accessing said data bus to communicate said parallel data value,

wherein said serial-to-parallel interface logic circuit further comprises;

a shift register for receiving a serial data value, said shift register having a parallel output bus;

a clock generator for receiving an external serial clock signal synchronized with said serial data value, said clock generator generating a plurality of interface serial clock pulses in response to said external serial clock signal, wherein said shift register clocks in said serial data value in response to said plurality of interface serial clock pulses;

a state machine, wherein said state machine generates a row/column address signal in response to said plurality of interface serial clock pulses from said clock generator;

a multiplexer-with-latch for storing an address data value received on said parallel output bus of said shift register, said multiplexer-with-latch being selected for receiving said address data value in response to said row/column address signal from said state machine;

an address counter for selecting an address on the parallel address bus of said serial-to-parallel interface logic circuit, wherein said address counter receives an initial address value from said address data value stored in said multiplexer-with-latch, said address counter incrementing the initial address value in response to an address counter increment signal;

a command logic circuit for receiving a command value from said parallel output bus of said shift register, said command logic decoding said command value to select one of a read operation and a write operation, said command logic circuit generating an operation select signal in response to said command value;

a read data buffer for receiving a second data value from the parallel data bus of said serial-to-parallel interface logic, said read data buffer operable for sending said second data value out a serial data line, said second data value being clocked onto said serial data line in response to said plurality of interface serial clock pulses from said clock generator;

a read/write state machine for receiving said operation select signal from said command logic circuit, said read/write state machine sending a control signal to the parallel data bus of said serial-to-parallel interface logic, and an enable signal to said read data buffer in response thereto, wherein said read/write state machine receives said plurality of interface serial clock pulses from said clock generators, and said row/column address signal from said state machine, said read/write state machine sending said address counter increment signal to said address counter in response thereto; and

a data logic circuit for receiving the serial data value from said parallel output bus of said shift register, said data logic circuit operable for selecting in response to said row/column address signal, and outputting said serial data value on said parallel data bus of said serial-to-parallel interface logic circuit.