Sourceless floating gate memory device and method of storing data

• US 5,814,853 A
• Filed: 01/22/1996
• Issued: 09/29/1998
• Est. Priority Date: 01/22/1996
• Status: Expired due to Term

• Current Assignee: Cypress Semiconductor Corporation (Infineon Technologies AG)
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Chen, Jian
• Primary Examiner(s): MINTEL, WILLIAM A
• Application Number:
  US08/589,750
• Time in Patent Office: 981 Days
• Field of Search: 257/315, 257/322, 257/314, 257/318, 257/321, 257/317, 365/175, 365/177, 365/182, 365/184
• US Class Current: 257/315
• CPC Class Codes: G11C 16/02 electrically programmable
• CPC Class Codes: G11C 16/0416 comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
• CPC Class Codes: H01L 29/861 Diodes
• CPC Class Codes: H01L 29/8616 Charge trapping diodes
• CPC Class Codes: H10B 69/00 Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices

Abstract

A floating gate diode which can be used as a sourceless memory cell, and which may be arranged into an array of memory cells is disclosed. The floating gate diode comprises: a drain region formed in a substrate; an oxide overlying and associated with the drain region; and a floating gate overlying the oxide. Upon application of a voltage to the drain, a current between the drain and substrate is induced in proportion to an amount of electrons stored on the gate. The cells may be arranged into an array which comprises a substrate having a surface; a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate; an oxide region overlying the plurality of drain regions on the surface of the substrate; and a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions.

Claims

1. A sourceless memory cell, comprising:

a substrate having a surface;

a drain region formed in the substrate;

a first oxide overlying the drain region on the surface of the substrate;

a first floating gate overlying the oxide;

wherein data is stored in the cell by an addition or removal of a charge accumulation on the floating gate, such that upon application of a negative potential applied to the floating gate and a positive potential applied to the drain, a read current between the drain and substrate is induced in proportion to an amount of electrons stored on the gate.

2. The memory cell of claim 1 wherein the substrate is a p-type substrate.

3. The memory cell of claim 1 wherein the substrate includes an n-well, and the drain is formed in the n-well of the substrate.

4. The memory cell of claim 1 wherein the substrate is an n-type substrate.

5. The memory cell of claim 1 wherein the substrate includes a p-well, and the drain is formed in the p-well of the substrate.

6. The memory cell of claim 3 further including a second oxide region overlying the drain region, and a second floating gate overlying the second oxide and respectively associated with said drain region.

11. The memory cell of claim 3 wherein a charged state of the cell varies from a threshold voltage range of about -0.5 volts to 3.5 volts, and the difference in said read current varies about 4 order of magnitude over said threshold voltage range.

12. The memory cell of claim 3 wherein the floating gate has first and second ends and wherein the floating gate is tapered at said first and second ends so that the thickness of the oxide at the ends of the gate is greater than at the middle of the gate.

7. A memory array comprising a plurality of cells, the array comprising:

a substrate having a surface;

a plurality of drain regions, one of said drain regions respectively corresponding to one of the plurality of cells, formed in the substrate;

an oxide region overlying the plurality of drain regions on the surface of the substrate;

a plurality of floating gates overlying the oxide and respectively associated with the plurality of drain regions;

wherein data is stored on each of the plurality of cells by an addition or removal of a charge accumulation on each floating gate, such that upon application of a positive voltage to the drain, and a negative voltage to the floating gate a current between the drain and the substrate is induced in proportion to an amount of electrons stored on the gate.

8. The memory array of claim 7 wherein one of said plurality of drain regions and one of said plurality of oxide regions is respectively associated with two of said plurality of floating gates.

9. The memory array of claim 7 further including control means for applying a current to the drain and gate to determine whether charge is trapped on any one of said floating gates.

10. A memory cell, consisting of:

a drain region formed in a substrate;

a gate oxide on the substrate, the gate oxide having a thickness; and

a floating gate comprised of a semiconductor material on the gate oxide, the floating gate having a first and a second end, wherein the semiconductor material is tapered at said first and second ends such that the thickness of the gate oxide at the ends of the floating gate is greater than at the middle of the gate.