Vertical power MOSFET having reduced sensitivity to variations in thickness of epitaxial layer

• US 5,814,858 A
• Filed: 03/15/1996
• Issued: 09/29/1998
• Est. Priority Date: 03/15/1996
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K.
• Primary Examiner(s): WOJCIECHOWICZ, EDWARD JOSEPH
• Application Number:
  US08/616,393
• Time in Patent Office: 928 Days
• Field of Search: 257/328, 257/332, 257/341, 257/401, 257/549, 437/20, 437/40, 438/228
• US Class Current: 257/328
• CPC Class Codes: H01L 29/0626 with a localised breakdown region, e.g. built-in avalanching region in self-protected thyristors H01L29/7424
• CPC Class Codes: H01L 29/0847 of field-effect transistors with insulated gate H01L29/0653 takes precedence; with a passive supplementary region between source or drain and substrate related to punch-through, capacity or isolation phenomena H01L29/1079; with LDD or DDD structure H01L29/7833; for thin film transistors H01L29/78618
• CPC Class Codes: H01L 29/0878 Impurity concentration or distribution
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7808 the other device being a breakdown diode, e.g. Zener diode
• CPC Class Codes: H01L 29/7811 with an edge termination structure guard regions per se H01L29/0619; field plates per se H01L29/402
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/7828 without inversion channel, e.g. vertical ACCUFETs, normally-on vertical MISFETs

Abstract

A vertical power MOSFET, which could be a trench-gated or planar double-diffused device, includes an N+ substrate and an overlying N-epitaxial layer. An N-type buried layer is formed in the epitaxial layer and overlaps the substrate, the buried layer having a dopant concentration which is greater than the dopant concentration of the epitaxial layer but less than the dopant concentration of the substrate. The ion implant which is used to create the buried layer is preferably performed after most of the high temperature operations in the fabrication process in order to minimize the diffusion of the buried layer. This controls the distance between the top edge of the buried layer and the drain-body junction of the MOSFET and allows the breakdown voltage and on-resistance of the MOSFET to be determined substantially without regard to the thickness of the epitaxial layer.

Claims

1. A vertical trench-gated power MOSFET comprising:

a semiconductor substrate of a first conductivity type;

an epitaxial layer formed on said substrate;

a gate formed in a trench extending downward from a surface of said epitaxial layer;

a source region of said first conductivity type formed in said epitaxial layer adjacent said surface thereof;

a body region of a second conductivity type opposite to said first conductivity type formed in said epitaxial layer adjacent said source region and a wall of said trench, said source and body regions being formed in a cell of said MOSFET bordered on at least two sides by said trench;

a drain which comprises said substrate and a portion of said epitaxial layer located adjacent said body region, said portion of said epitaxial layer being doped with ions of said first conductivity type to a first concentration level; and

a buried layer formed within said epitaxial layer and extending continuously across said cell, said buried layer having an upper edge that is located at a level above an interface between said substrate and said epitaxial layer and a lower edge that is located at a level below said interface, a portion of said buried layer within said epitaxial layer being doped with ions of said first conductivity type to a second concentration level which is greater than said first concentration level.

2. The power MOSFET of claim 1 wherein the upper edge of said buried layer is located at a level below a bottom of said trench.

3. The power MOSFET of claim 2 further comprising a diffusion of said second conductivity type extending downward from said surface of said epitaxial layer outside of an active MOSFET cell of said power MOSFET.

4. The power MOSFET of claim 2 further comprising a diffusion of said second conductivity type extending downward from said body region in a central region of an active MOSFET cell of said power MOSFET.

5. The power MOSFET of claim 2 further comprising a plug region within said epitaxial layer adjoining an upper edge of said buried layer, said plug region being located beneath said body region in a central area of an active MOSFET cell of said power MOSFET and being doped with ions of said first conductivity type to a third concentration level which is greater than said first concentration level and which may be equal to said second concentration level.

6. The power MOSFET of claim 1 wherein the upper edge of said buried layer is located at a level above a bottom of said trench.

7. The power MOSFET of claim 1 wherein said buried layer does not extend into a edge termination area of said power MOSFET.

8. The power MOSFET of claim 1 further comprising a body contact region adjacent said surface of said epitaxial layer.

9. The power MOSFET of claim 8 further comprising a metal layer shorting said source region and said body contact region together.

10. The power MOSFET of claim 1 wherein said body region does not extend to a surface of said epitaxial layer within an active MOSFET cell.

11. The power MOSFET of claim 10 wherein said body region within said active MOSFET cell is substantially fully depleted of charge carriers when said gate is biased so as to turn said power MOSFET off.

12. The power MOSFET of claim 1, wherein the upper edge of said buried layer is located at a level below a bottom of said trench.

13. The power MOSFET of claim 1, wherein the upper edge of said buried layer is located at a level above a bottom of said trench.

14. A process of fabricating a MOSFET comprising the steps of:

forming an epitaxial layer on a surface of a semiconductor substrate, said epitaxial layer having a substantially planar top surface, both of said substrate and said epitaxial layer being doped with ions of a first conductivity type, said substrate being doped to a greater concentration level than said epitaxial layer;

implanting ions of said first conductivity type through said top surface of said epitaxial layer so as to form a buried layer of said first conductivity type;

forming a trench extending downward from said surface of said epitaxial layer;

forming a dielectric layer on a wall of said trench;

filling said trench with a conductive gate material, said gate material being electrically insulated from said epitaxial layer by said dielectric layer;

forming a body region of a second conductivity type opposite to said first conductivity type in said epitaxial layer; and

forming a source region of said first conductivity type in said epitaxial layer;

wherein at the completion of said process an upper edge of said buried layer is at a level that is located above an interface between said substrate and said epitaxial layer and a lower edge of said buried layer is at a level that is located below said interface.

15. The process of claim 14 wherein said buried layer is formed before said trench is formed.

16. The process of claim 14 wherein said buried layer is formed after said body region is formed but before said source region is formed.

17. The process of claim 14 wherein said buried layer is formed after said source region is formed.

18. The process of claim 14 comprising the further step of forming a body contact region in said epitaxial layer, said buried layer being formed after the formation of said body contact.

19. The process of claim 14 comprising the further step of forming an oxide layer over said trench, said buried layer being formed after the formation of said oxide layer.

23. The process of claim 14 further comprising the step of heating said substrate and said epitaxial layer thereby to diffuse said ions of said first conductivity type in said buried layer and increase the thickness of said buried layer.

20. A process of fabricating a MOSFET comprising the steps of:

forming an epitaxial layer on a surface of a semiconductor substrate, said epitaxial layer having a substantially planar top surface, both of said substrate and said epitaxial layer being doped with ions of a first conductivity type, said substrate being doped to a greater concentration level than said epitaxial layer;

implanting ions of said first conductivity type through said top surface of said epitaxial layer so as to form a buried layer of said first conductivity type;

forming a dielectric layer on said surface of said epitaxial layer;

forming a gate over said dielectric layer;

forming a body region of a second conductivity type opposite to said first conductivity type in said epitaxial layer; and

forming a source region of said first conductivity type in said epitaxial layer;

wherein at the completion of said process an upper edge of said buried layer is at a level that is located above an interface between said substrate and said epitaxial layer and a lower edge of said buried layer is at a level that is located below said interface.

21. The process of claim 20 wherein said buried layer is formed before said gate is formed.

24. The process of claim 20 further comprising the step of heating said substrate and said epitaxial layer thereby to diffuse said ions of said first conductivity type in said buried layer and increase the thickness of said buried layer.

22. A process of fabricating a MOSFET comprising the steps of:

providing a semiconductor substrate doped with ions of first conductivity type;

implanting ions of said first conductivity type into said substrate so as to form a layer of said first conductivity type within said substrate;

forming an epitaxial layer on a surface of said semiconductor substrate, said epitaxial layer being doped with ions of said first conductivity type;

allowing ions within said layer of said first conductivity type to diffuse across an interface between said substrate and said epitaxial layer;

forming a trench extending downward from said surface of said epitaxial layer;

forming a dielectric layer on a wall of said trench;

filling said trench with a conductive gate material, said gate material being electrically insulated from said epitaxial layer by said dielectric layer;

forming a body region of a second conductivity type opposite to said first conductivity type in said epitaxial layer; and

forming a source region of said first conductivity type in said epitaxial layer;

wherein at the completion of said process said layer of ions of said first conductivity type extends across an interface between said substrate and said epitaxial layer downward to a level below said interface and upward to a level above a bottom of said trench.

25. The process of claim 22 further comprising the step of heating said substrate and said epitaxial layer thereby to diffuse said ions in said layer of said first conductivity type and increase the thickness of said layer of said first conductivity type.