Duty cycled control implemented within a frequency synthesizer
First Claim
1. A programmable frequency synthesizer comprising:
- (a) a phase locked loop (PLL) including a current controlled oscillator (ICO),(b) a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate,(c) a reference source of signals,(d) a phase-frequency detector for receiving signals from said reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and(e) means for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied.
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Abstract
A programmable frequency synthesizer comprised of a phase locked loop (PLL) including a current controlled oscillator (ICO), a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate, a reference source of signals, a phase-frequency detector for receiving signals from the reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and apparatus for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied.
63 Citations
15 Claims
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1. A programmable frequency synthesizer comprising:
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(a) a phase locked loop (PLL) including a current controlled oscillator (ICO), (b) a level translator for receiving output signals from the ICO wherein the output signals have a finite slew rate, (c) a reference source of signals, (d) a phase-frequency detector for receiving signals from said reference source and output signals generated by the level translator and for providing pulse signals to the ICO having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the level translator, and (e) means for varying the slew rate of the output signals from the ICO wherein the duty cycle and thus the frequency of output signals of the level translator may be varied. - View Dependent Claims (2, 3, 4, 5, 6)
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7. A programmable frequency synthesizer comprising:
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(a) a phase locked loop (PLL) including a current controlled oscillator (ICO), (b) a reference source of signals, (c) a phase-frequency detector, (d) a circuit for applying signals from the reference source to an input of the phase frequency detector, (e) a circuit for applying signals derived from an output of the PLL to another input of the phase-frequency detector, (f) a circuit for providing output signals from the phase-frequency detector to the ICO which are directly proportional to a phase difference between the signals from the reference source and the signals derived from an output of the PLL, and (g) means for varying the slew rate of output signals from the ICO wherein the duty cycle of the output signals may be varied. - View Dependent Claims (8, 9, 10)
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11. A programmable frequency synthesizer comprising a phase locked loop (PLL) including a current control oscillator (ICO) which generates a digital clock signal, the frequency of which is controlled by input current to the ICO, a level transistor which has a finite output slew rate for translating reduced swing output signals from the ICO into fully digital signals, an output buffer for buffering the output of the level translator, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the output buffer and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the output of the output buffer, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current applied to the ICO for control thereof, and apparatus for varying the slew rate of the output signals from the level translator wherein the duty cycle of the output signals may be varied.
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12. A programmable frequency synthesizer comprising a phase locked loop (PLL) including a current controlled oscillator (ICO) which has an internal signal with a finite slew rate, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the ICO and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals form the reference source and the output signals from the output from the ICO, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current that controls the ICO, and apparatus for varying the slew rate of a signal within the ICO wherein the duty-cycle of the output signals may be varied.
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13. A programmable frequency synthesizer comprising a phase locked loop (PLL) including a voltage controlled oscillator (VCO) which has an internal signal with a finite output slew rate, a reference source of clock signals, a phase-frequency detector (PFD) for receiving output signals from said reference source and the output from the VCO and for generating voltage pulse signals having pulse widths which are directly proportional to phase difference between the signals from the reference source and the output signals from the output from the VCO, a charge pump for converting output voltage pulses from the PFD into output current pulses, a loop filter for converting output current pulses from the charge pump into a bias voltage and for providing the PLL with high order damping, a voltage to current converter for mapping the output bias voltage from the loop filter into bias current that controls the ICO, and apparatus for varying the slew rate of a signal within the VCO wherein the duty-cycle of the output signals may be varied.
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14. A method of synthesizing a signal comprising providing a phase locked loop having a current controlled oscillator (ICO), selectively varying the slew rate of an output signal of the ICO to thereby vary the duty cycle thereof, the selectively varying step including selecting an amount of current derived from the output signal of the ICO and providing the selected amount of current to a feedback loop of the phase locked loop, the selectively varying step is comprised of switching FETs in parallel to carry said current derived from the output signal, thereby sourcing increased current to the feedback loop when an output voltage of the ICO is rising, or draining increased current from the feedback loop when the output voltage of the ICO is falling.
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15. A method of synthesizing a signal comprising synthesizing a pulse signal within a phase locked loop and selectively varying the slew rate of said signal within the phase locked loop vary the duty cycle of said signal, the phase locked loop including a voltage controlled oscillator (VCO) and means for varying the slew rate of a signal within the VCO.
Specification