Delta sigma pwm dac to reduce switching

• US 5,815,102 A
• Filed: 06/12/1996
• Issued: 09/29/1998
• Est. Priority Date: 06/12/1996
• Status: Expired due to Term

• Current Assignee: Cirrus Logic Incorporated
• Original Assignee: AudioLogic, Inc. (Cirrus Logic Incorporated)
• Inventors: Melanson, John Laurence
• Primary Examiner(s): Williams, Howard L.
• Application Number:
  US08/662,873
• Time in Patent Office: 839 Days
• Field of Search: 341/152, 341/143, 341/144, 341/131, 341/77, 341/53
• US Class Current: 341/143
• CPC Class Codes: G06F 1/025 for functions having two-valued amplitude, e.g. Walsh functions
• CPC Class Codes: H03M 3/388 by storing corrected or correction values in one or more digital look-up tables
• CPC Class Codes: H03M 3/506 the final digital/analogue converter being constituted by a pulse width modulator
• CPC Class Codes: H03M 7/3026 the quantiser being a multiple bit one
• CPC Class Codes: H03M 7/304 with distributed feedback, i.e. with feedback paths from the quantiser output to more than one filter stage

Abstract

A digital to analog (D/A) converter for hearing aids and the like includes a delta sigma modulator and a duty cycle demodulator. The delta sigma modulator converts medium rate, high resolution data into medium rate, medium resolution data, and the duty cycle demodulator converts the medium rate, medium resolution data into low resolution, high rate data. The duty cycle demodulator utilizes a lookup function to format the output data in a format having lowered transition rates, resulting in lower power use. The delta sigma converter may include a correction factor in at least one of its feedback loops to compensate for the characteristics of the output data from the duty cycle demodulator.

Claims

1. In a delta sigma quantizer of at least second order including at least two accumulators having accumulator arithmetic elements for adding delayed output signals from the accumulator arithmetic elements to input signals provided to the accumulator arithmetic elements, said accumulators providing signals to a quantizer which provides output signals and feedback signals to the accumulators, said delta sigma modulator further including feedback arithmetic elements for adding said feedback signals to the accumulator input signals, the improvement comprising:

a single multiport adder operating in multiple phases comprises the accumulator arithmetic elements and the feedback arithmetic elements.

2. The delta sigma modulator of claim 1 wherein the single multiport adder comprises a three input adder operating in three phases.

3. The delta sigma modulator of claim 2 wherein the three phases comprise:

the first phase adds the input to the delta sigma modulator plus the previous output of the first stage plus the negative of the feedback;

the second phase adds the current output of the first stage plus the previous output of the second stage; and

the third phase adds the current output of the first stage plus the current output of the second stage, and feeds the quantizer.

4. A digital to analog demodulator including the delta sigma quantizer of claim 1 and further comprising:

a duty cycle demodulator connected to the delta sigma modulator for converting the output of the quantizer into a higher rate lower resolution signal; and

D/A means connected to the duty cycle demodulator for converting the higher rate lower resolution signal into an analog signal;

wherein the duty cycle demodulator includes means for formatting the higher rate medium resolution signal into a predetermined low transition rate format.

5. A digital to analog demodulator including the delta sigma quantizer of claim 3 and further comprising:

a duty cycle demodulator connected to the delta sigma for converting modulator the output of the quantizer into a higher rate lower resolution signal; and

D/A means connected to the duty cycle demodulator for converting the higher rate lower resolution signal into an analog signal;

wherein the duty cycle demodulator includes means for formatting the higher rate medium resolution signal into a predetermined low transition rate format.

6. The digital to analog converter of claim 5, wherein the delta sigma modulator further includes:

means for selecting a correction factor to be applied to at least one of the feedback signals based upon the predetermined low transition rate format and the feedback signal; and

means for applying the correction factor to at least one of the feedback loops.

7. A second order delta sigma quantizer comprising:

means for applying an input signal to the delta sigma quantizer;

a first accumulator comprising means for storing a previous value of said first accumulator'"'"'s output, and means for adding at least one other input to the previous value of said first accumulator'"'"'s output, to form said first accumulator'"'"'s current output;

a second accumulator comprising means for storing a previous value of said second accumulator'"'"'s output, and means for adding at least one other input to the previous value of said second accumulator'"'"'s output, to form said second accumulator'"'"'s current output;

an adder for adding at least two inputs to form an adder output;

a quantizer for quantizing the adder output to generate a standard feedback signal and an output signal; and

correction means for receiving the standard feedback signal and generating a corrected feedback signal to account for nonlinear higher integrals of the output data patterns;

wherein the other inputs to the first accumulator comprise the standard feedback signal and the input signal, the other inputs to the second accumulator comprise the current output of the first accumulator and the corrected feedback signal, and the inputs to the adder comprise the current output of the first accumulator fed forward and the current output of the second accumulator.

8. The second order delta sigma quantizer of claim 7, further comprising:

dither means for providing a dither signal as an input to the adder.

9. A digital to analog (D/A) converter for converting a medium rate, high resolution digital signal into an analog signal, said converter comprising:

a delta sigma modulator of at least second order including at least two feedback loops carrying a feedback signal for converting the medium rate, high resolution digital signal into a medium rate, medium resolution digital signal;

a duty cycle demodulator connected to the delta sigma modulator for converting the medium rate, medium resolution digital signal into a high rate, low resolution digital signal; and

D/A means connected to the duty cycle demodulator for converting the high rate, low resolution digital signal into the analog signal;

wherein the duty cycle demodulator includes means for formatting the high rate, low resolution digital signal into a predetermined low transition rate format; and

wherein the delta sigma modulator includes;

means for selecting different correction factors to be applied to at least two of the feedback loops based upon the predetermined low transition rate format and the feedback signal; and

means for applying different correction factors to at least two of the feedback loops.

10. The D/A converter of claim 9, wherein the duty cycle demodulator includes alternating means for alternating the predetermined low transition rate format between at least two different formats selected for successive outputs of the delta sigma modulator, for lowering the transition rate of the high rate low resolution signal further.

11. The D/A converter of claim 9, wherein the formatting means comprises:

means for determining a multiple bit value corresponding to each input value of the medium rate, medium resolution digital signal; and

means for outputting the determined values as the high rate, low resolution digital signal.

12. The D/A converter of claim 11, wherein said determining means comprises:

means for storing a value corresponding each possible input value of the medium rate, medium resolution digital signal, said stored value representing said corresponding input value formatted in the predetermined low transition rate format; and

lookup means responsive to each medium rate, medium resolution digital signal input for looking up the corresponding stored value.

13. The D/A converter of claim 12, wherein:

the determining means comprises a read-only-memory (ROM) said ROM outputting the looked up values in parallel; and

the means for outputting comprises a parallel to serial converter connected to said ROM, said parallel to serial converter converting the parallel looked up values into the high rate, low resolution digital signal.

14. The D/A converter of claim 9, wherein the D/A means comprises a class D output stage for driving an output speaker.

15. The D/A converter of claim 9, implemented in an integrated circuit.

16. The D/A converter of claim 9, implemented to operate at 1.1 volts or lower.

17. A digital to analog (D/A) converter for converting a medium rate, high resolution digital signal into an analog signal, said converter comprising:

a delta sigma modulator of at least second order including at least two feedback loops carrying a feedback signal for converting the medium rate, high resolution digital signal into a medium rate, medium resolution digital signal;

a duty cycle demodulator connected to the delta sigma modulator for converting the medium rate, medium resolution digital signal into a high rate, low resolution digital signal; and

D/A means connected to the duty cycle demodulator for converting the high rate, low resolution digital signal into the analog signal;

wherein the duty cycle demodulator includes means for formatting the high rate, low resolution digital signal into a predetermined low transition rate format; and

wherein the delta sigma modulator includes;

means for selecting a correction factor to be applied to only one of the feedback loops based upon the predetermined low transition rate format and the feedback signal; and

means for applying the correction factor to only one of the feedback loops.

18. The D/A converter of claim 17, wherein the duty cycle demodulator includes alternating means for alternating the predetermined low transition rate format between at least two different formats selected for successive outputs of the delta sigma modulator, for lowering the transition rate of the high rate low resolution signal further.

19. The D/A converter of claim 17, wherein the formatting means comprises:

means for determining a multiple bit value corresponding to each input value of the medium rate, medium resolution digital signal; and

means for outputting the determined values as the high rate, low resolution digital signal.

20. The D/A converter of claim 19, wherein said determining means comprises:

means for storing a value corresponding each possible input value of the medium rate, medium resolution digital signal, said stored value representing said corresponding input value formatted in the predetermined low transition rate format; and

lookup means responsive to each medium rate, medium resolution digital signal input for looking up the corresponding stored value.

21. The D/A converter of claim 20, wherein:

the determining means comprises a read-only-memory (ROM) said ROM outputting the looked up values in parallel; and

the means for outputting comprises a parallel to serial converter connected to said ROM, said parallel to serial converter converting the parallel looked up values into the high rate, low resolution digital signal.

22. The D/A converter of claim 17, wherein the D/A means comprises a class D output stage for driving an output speaker.

23. The D/A converter of claim 17, implemented in an integrated circuit.

24. The D/A converter of claim 17, implemented to operate at 1.1 volts or lower.

25. A hearing aid, of the type including an audio receiver to receive ambient sound, an analog to digital (A/D) converter to convert the sound to a high resolution, low rate digital signal, digital processing circuitry to modify the quality of the high resolution, low rate digital signal, interpolator circuitry for converting the high resolution, low rate digital signal to a medium rate, high resolution signal, a digital to analog (D/A) converter for converting the modified high resolution, medium rate digital signal back into analog sound, wherein the improvement is an improved demodulator within the D/A converter, said demodulator comprising:

a delta sigma modulator of at least second order, having at least two feedback loops carrying a feedback signal, for converting the high resolution, medium rate digital signal into a medium rate, medium resolution digital signal; and

a duty cycle demodulator connected to the delta sigma modulator for converting the medium rate, medium resolution digital signal into a high rate, low resolution digital signal;

wherein the duty cycle demodulator includes means for formatting the high rate, low resolution digital signal into a predetermined low transition rate format; and

wherein said delta sigma modulator further includes;

means for selecting and applying two different correction factors to two of the feedback loops based upon the predetermined low transition rate format and the feedback signal.

26. A hearing aid, of the type including an audio receiver to receive ambient sound, an analog to digital (A/D) converter to convert the sound to a high resolution, low rate digital signal, digital processing circuitry to modify the quality of the high resolution, low rate digital signal, interpolator circuitry for converting the high resolution, low rate digital signal to a medium rate, high resolution signal, a digital to analog (D/A) converter for converting the modified high resolution, medium rate digital signal back into analog sound, wherein the improvement is an improved demodulator within the D/A converter, said demodulator comprising:

a delta sigma modulator of at least second order, having at least two feedback loops carrying a feedback signal, for converting the high resolution, medium rate digital signal into a medium rate, medium resolution digital signal; and

a duty cycle demodulator connected to the delta sigma modulator for converting the medium rate, medium resolution digital signal into a high rate, low resolution digital signal;

wherein the duty cycle demodulator includes means for formatting the high rate, low resolution digital signal into a predetermined low transition rate format; and

wherein said delta sigma modulator further includes;

means for selecting and applying a correction factor to only one of the feedback loops based upon the predetermined low transition rate format and the feedback signal.