Method and apparatus for providing concurrent access by a plurality of agents to a shared memory

• US 5,815,167 A
• Filed: 06/27/1996
• Issued: 09/29/1998
• Est. Priority Date: 06/27/1996
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Muthal, Manish, Shah, Nilesh V., Bains, Kuljit
• Primary Examiner(s): Bayerl, Raymond J.
• Assistant Examiner(s): Nguyen, Cao H.
• Application Number:
  US08/672,099
• Time in Patent Office: 824 Days
• Field of Search: 395/501, 395/502, 395/508, 395/512, 395/515, 395/201, 395/511
• US Class Current: 345/541
• CPC Class Codes: G06F 13/1647 with interleaved bank access
• CPC Class Codes: G06F 15/167 using a common memory, e.g. mailbox

Abstract

A computer system, including a graphics controller and a memory controller, employs a Shared Frame Buffer Architecture, and accordingly has a shared memory in the form a bank of DRAMs. The shared memory is accessible by both the memory and graphics controllers. The memory includes a shared DRAM row in which a Shared Frame Buffer (SFB) aperture is defined. An interface selectively provides access to the shared DRAM row by the graphics or memory controller, while providing permanent access to the remaining DRAM rows by the memory controller. This facilitates concurrent access by the graphics controller and the memory controller to the shared DRAM row and to the remaining DRAM rows respectively, in a first memory access scenario. The accessibility of the shared DRAM row by the memory controller, in a second memory access scenario, is also maintained. The interface includes a selector circuit, such as a multiplexor or Q-switch, coupled to receive memory address signals and control signals from the graphics controller and the memory controller via a dedicated bus from each of these controllers. The selector circuit is operable selectively to present either memory address to the shared DRAM row, in which the SFB aperture is defined, and also selectively to provide access to the shared DRAM row by either controller. The selector circuit is operable by a logic circuit, incorporated within the systems controller, which determines whether a memory access request received from the memory controller is to an address in the shared DRAM row, or in the remaining DRAM rows.

Claims

1. A computer system comprising:

first and second agents;

a shared memory accessible by the first and second agents, the shared memory having a first memory portion and a second memory portion, at least a portion of the second memory portion to store data associated exclusively with the second agent; and

a switch arrangement to provide (i) a first data path between the first agent and the second memory portion when in a first state, and to provide (ii) a second data path between the first agent and the first memory portion and (iii) a third data path between the second agent and the second memory portion when in a second state, the second and third data paths being distinct and provided in parallel so as to facilitate simultaneous access to the first and second memory portions by the first and second agents respectively when the switch arrangement is in the second state.

2. The computer system of claim 1 wherein the switch arrangement is coupled to receive first and second memory addresses from the first and second agents respectively, and operable selectively to provide the first memory address to the second memory portion when in the first state, and to provide the second memory address to the second memory portion when in the second state.

3. The computer system of claim 2 including a logic circuit for determining whether the first memory address received from the first agent is in the first memory portion and, if so, configuring the switch arrangement to operate in the second state.

4. The computer system of claim 1 wherein the first agent is a memory controller and the second agent is a graphics controller.

5. The computer system of claim 1 wherein the shared memory comprises a plurality of rows of random access memory (RAM), and wherein the first memory portion comprises a first row of RAM, and the second memory portion comprises a second row of RAM.

6. The computer system of claim 5 wherein the second row of RAM incorporates a frame buffer aperture.

7. The computer system of claim 6 wherein the frame buffer aperture is located in a low memory address range within the shared memory.

8. An interface arrangement for a shared memory, the shared memory having first and second memory portions, the interface comprising:

a first input coupled to receive a first memory address from a first agent;

a second input coupled to receive a second memory address from a second agent;

a selector operable selectively to present the second memory address to the second memory portion when in a first state so as to facilitate simultaneous access by the first agent to the first memory portion via a first access path and by the second agent to the second memory portion via a second access path and selectively to present the first memory address to the second memory portion when in a second state so as to facilitate exclusive access by the first agent to at least the second memory portion via a third access path, the first and second access paths being distinct and existing in parallel to facilitate the simultaneous access.

9. The interface arrangement of claim 8 wherein the selector is coupled to be operable by logic circuitry to determine whether a memory address presented to the logic circuitry by the first agent is located in either the first or second memory portion.

10. The interface arrangement of claim 8 wherein the selector includes a first switch coupled to receive address and control inputs from the first and second agents and operable selectively to provide address and control input from the first agent to the second memory portion when the selector is in the second state, and to the first memory portion when the selector is in the first state.

11. The interface arrangement of claim 10 wherein the selector includes a second switch operable selectively to receive data from, and transmit data to, either the first or the second memory portion.

12. A method of facilitating simultaneous access by first and second agents to a shared memory via a memory interface, the shared memory including first and second memory portions, the method including the steps of:

(a) receiving a memory access request from the first agent;

(b) determining whether the memory access request of the first agent is to a memory location in the first or second memory portion of the shared memory;

(c) if the memory access request of the first agent is to a memory location in the first memory portion, placing the memory interface in a first state in which the first agent has access to the first memory portion via a first access path and in which the second agent is able to access the second memory portion via a second access path, the first and second access paths being distinct and existing in parallel to facilitate simultaneous access by the first and second agents to the first and second memory portions respectively; and

(d) if the memory access request of the first agent is to a memory location in the second memory portion, placing the memory interface in a second state in which the first agent has exclusive access to at least the second memory portion via a third access path.

13. The method of claim 12 wherein only the second memory portion of the shared memory is shared by the first and second agents, and wherein the method includes the steps of:

if the memory access request of the first agent is to a memory location in the second memory portion, determining whether a memory access request to a memory location in the second memory portion from the second agent is outstanding; and

if a memory access request from the second agent is outstanding, arbitrating between the access requests of the first and second agents.

14. The method of claim 12 including the steps of:

receiving a memory access request from the second agent to a memory location in the second memory portion of the shared memory;

determining whether the first agent is accessing a memory location in the second memory portion; and

if the first agent is not accessing the second memory portion, then placing the memory interface in the first state and granting the second agent access to the second portion so that the first agent is simultaneously able to access the first memory portion.

15. The method of claim 14 including the step of denying the second agent access to the second portion if the first agent is accessing a memory location in the second memory portion.

16. The method of claim 14 including the step of arbitrating between the access requests of the first and second agents if the first agent is accessing a memory location in the second memory portion.