Image forming processor having first and second image processing sections

• US 5,815,287 A
• Filed: 11/06/1995
• Issued: 09/29/1998
• Est. Priority Date: 11/10/1994
• Status: Expired due to Term

• Current Assignee: Minolta Co., Ltd. (Konica Minolta Inc.)
• Original Assignee: Minolta Co., Ltd. (Konica Minolta Inc.)
• Inventors: Yamada, Hirokazu
• Primary Examiner(s): Coles, Sr., Edward L.
• Assistant Examiner(s): BRINICH, STEPHEN M
• Application Number:
  US08/554,411
• Time in Patent Office: 1,058 Days
• Field of Search: 358/429, 358/456-459, 358/465-467, 358/534-536
• US Class Current: 358/448
• CPC Class Codes: H04N 1/40062 Discrimination between different image types, e.g. two-tone, continuous tone
• CPC Class Codes: H04N 1/4055 producing a clustered dots or a size modulated halftone pattern

Abstract

An image processor for parallel image processing includes a first image processing section which binarizes first image data by using a variable area tone method and a second image processing section which executes a smoothing process with respect to second image data. A data separator divides image data into first image data corresponding to halftone image regions and second image data corresponding to binary image regions. The first image data is transmitted to the first image processing section while the second image data is transmitted to the second image processing section. A data delay section is provided at an upstream side of the first image processing section to delay image data for the required processing time difference between the first image process and the second image process. A data combining section combines the image data output from the first image processing section and the second image processing section to produce combined image data which is transmitted to an image forming system.

Claims

1. An image processor comprising:

a first image processing section for accomplishing a first image process of image data input synchronously with first clock signals, and which outputs first processed image data synchronously with second clock signals having a frequency higher than said first clock signals;

a second image processing section for accomplishing a second image process of image data input synchronously with said first clock signals, and which processes in parallel with said first image process and outputs second processed image data synchronously with said second clock signals;

a data combining section for combining image data respectively output from said first image processing section and said second image processing section; and

a data delay section provided at an upstream side of said first image processing section to delay image data for a period of time corresponding to a difference in required processing times between said first image process and said second image process.

2. The image processor as claimed in claim 1, further comprising a data separator for dividing image data into first image data corresponding to halftone image regions and second image data corresponding to binary image regions, said first image data being transmitted to said first image processing section and said second image data being transmitted to said second image processing section.

3. The image processor as claimed in claim 2, wherein said first image processing section binarizes the first image data by using a variable area tone method, and said second image processing section executes a smoothing process with respect to the second image data.

4. The image processor as claimed in claim 3, wherein said first image processing section includes a pattern memory for storing a plurality of dither patterns, one of said dither patterns being selected in accordance with a value of the first image data.

5. The image processor as claimed in claim 4, wherein said value is a density value.

6. The image processor as claimed in claim 2, wherein said data separator divides image data in accordance with a value of the image data.

7. The image processor as claimed in claim 6, wherein said value is a density value.

8. An image processor comprising:

generating means for generating dot image data to be printed;

printing means for printing an image line by line in accordance with said dot image data;

data dividing means for dividing said dot image data into first dot image data and second dot image data;

a first image processing section for receiving the first dot image data synchronously with first clock signals, accomplishing a first image process with respect to said first dot image data, and outputting processed first image data synchronously with second clock signals having a frequency higher than said first clock signals;

a second image processing section for receiving the second dot image data synchronously with said first clock signals, accomplishing a second image process with respect to said second dot image data in parallel with said first image process, and outputting processed second image data synchronously with said second clock signals;

a data combining section for combining processed first and second image data respectively output from said first image processing section and said second image processing section and transmitting combined image data to said printing means; and

a data delay section provided at an upstream side of said first image processing section to delay image data for a period of time corresponding to a difference in required processing times between said first image process and said second image process.

9. The image processor as claimed in claim 8, wherein said first dot image data corresponds to halftone image regions and said second image data corresponds to binary image regions.

10. The image processor as claimed in claim 9, wherein said first image processing section binarizes the first dot image data by using a variable area tone method, and said second image processing section executes a smoothing process with respect to the second dot image data.

11. The image processor as claimed in claim 10, wherein said first image processing section includes pattern memory for storing a plurality of dither patterns, one of said dither patterns being selected in accordance with a value of the first image data.

12. The image processor as claimed in claim 11, wherein said value is a density value.

13. The image processor as claimed in claim 8, wherein said data dividing means divides image data in accordance with a value of the dot image data.

14. The image processor as claimed in claim 13, wherein said value is a density value.

15. The image processor as claimed in claim 8, wherein said dividing means includes line delay section for delaying the first dot image data for predetermined number of lines, and dot delay section for delaying the first dot image data for predetermined number of dots.

16. The image processor as claimed in claim 15, wherein said line delay section has a FIFO memory and said dot delay section has a shift register.

17. An image processor comprising:

a first image processing section for processing to achieve tone reproduction relative to multi-level image data expressing the density of each picture element;

a second image processing section for processing to achieve smoothing relative to binary image data obtained by binarizing said image data;

a data separator for outputting said image data less than a predetermined density value to said first image processing section, and outputting image data equal to said predetermined density value to said second image processing section; and

a data combining section for combining image data respectively output from said first image processing section and said second image processing section.

18. The image processor as claimed in claim 17, wherein said predetermined density value is a maximum density value.

19. An image processor comprising:

a first image processing section for processing to achieve tone reproduction relative to multi-level image data expressing the density of each picture element;

a second image processing section for processing to achieve smoothing relative to binary image data obtained by binarizing said image data;

a data separator for outputting said image data less than a predetermined density value to said first image processing section, and outputting image data equal to said predetermined density value to said second image processing section; and

a data combining section for combining image data respectively output from said first image processing section and said second image processing section;

wherein said first image processing section binarizes the image data by using a variable area tone method.

20. The image processor as claimed in claim 19, wherein said first image processing section includes pattern memory for storing a plurality of dither patterns, one of said dither patterns being selected in accordance with a density value of the first image data.