Integrated circuit input/output ESD protection circuit with gate voltage regulation and parasitic zener and junction diode

• US 5,815,360 A
• Filed: 12/06/1996
• Issued: 09/29/1998
• Est. Priority Date: 01/12/1994
• Status: Expired due to Term

• Current Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Consiglio, Rosario, Sparacino, Gina M.
• Primary Examiner(s): Young, Brian K.
• Assistant Examiner(s): JACKSON, STEPHEN W
• Application Number:
  US08/761,443
• Time in Patent Office: 662 Days
• Field of Search: 361/56, 361/91, 361/118, 361/111
• US Class Current: 361/118
• CPC Class Codes: H01L 27/0251 for MOS devices
• CPC Class Codes: H02H 9/046 responsive to excess voltage appearing at terminals of integrated circuits protection by specific structural integration design H01L27/0248
• CPC Class Codes: H03K 19/00315 in field-effect transistor circuits

Abstract

An integrated circuit structure with input/output gate voltage regulation and parasitic zener and junction diodes for protection against damage resulting from electrostatic discharge (ESD) events. The circuit includes a first protective FET connected between an input/output pad and a ground potential of the integrated circuit. A diode voltage regulator is also connected between the gate of the first protective FET and a reference potential of the integrated circuit. The first protective FET receives a voltage from its gate-drain overlap capacitance during an ESD event. The diode is operative during an ESD event to provide a sufficient voltage to the first FET gate to permit a desired ESD current flow through the first protective FET. In one embodiment the first FET is an NMOS device and the diode voltage regulator is a series of p-n forward biased diodes.

Claims

1. An electro-static discharge protection circuit adapted for use in an integrated circuit comprising:

a first protective field effect transistor connected between a pad of said integrated circuit and a potential of said integrated circuit and having a gate, said first transistor responsive to a voltage applied to said gate to control a current through said first transistor; and

a voltage regulator connected between said gate of said first protective transistor and said potential of said IC, said diode voltage regulator operative to apply said voltage to said gate such that a desired amount of current flows through said first transistor when an electro-static discharge is applied to said pad.

2. The circuit of claim 1 wherein said diode voltage regulator includes at least one p-n junction diode connected between said gate and said potential.

3. The circuit of claim 1 wherein said voltage regulator supplies a voltage to said gate of said first transistor in the range between about 1.0 and 2.5 volts dc.

4. The method of claim 1, wherein said first voltage regulator comprises:

a first diode having an anode connected to said gate of said first transistor, and a cathode;

a second diode having an anode connected to said cathode of said first diode, and a cathode; and

a third diode having an anode connected to said cathode of said second and a cathode connected to said ground potential of said integrated circuit.

5. The method of claim 4 further comprising:

connecting an additional diode, having an anode and a cathode, in series between said first and second diodes such that said anode of said additional diode is electrically connected between said cathode of said first diode and said anode of the second diode.

6. A method for performing electrostatic discharge protection in an integrated circuit, comprising:

connecting a first protective field effect transistor between a pad of the integrated circuit and a potential of said integrated circuit, said first transistor being responsive to a voltage applied to said gate thereby controlling a current through said first transistor;

connecting a voltage regulator between said gate of said first protective transistor and said potential of said integrated circuit, said voltage regulator having the ability to apply said voltage to said gate such that a predetermined amount of current flows through said first transistor when an electrostatic discharge is applied to said pad;

wherein said potential is a ground potential and said first protective transistor is an NMOS field effect transistor having a drain electrically connected to said ground potential.

7. The method of claim 6 wherein said first protective transistor is a spare transistor within the integrated circuit and is unused during normal integrated circuit operation.

8. The method of claim 7 wherein said resistor is an N-well resistor.

9. An electrostatic discharge circuit adapted for use in an integrated circuit, comprising:

a first protective field effect transistor connected between a pad of said integrated circuit and a potential of said integrated circuit and having a gate, said first transistor responsive to a voltage applied to said gate to control a current through said first transistor;

a voltage regulator connected between said gate of said first protective transistor and said potential of said integrated circuit, said voltage regulator operative to apply said voltage to said gate such that a predetermined amount of current flows through said first transistor when an electrostatic discharge is applied to said pad; and

a second protective field effect transistor having a gate electrically connected to said pad and said drain of said first protective transistor, a drain connected to said gate of said first transistor, and a source connected to said ground potential of said integrated circuit.

10. The circuit of claim 9, wherein said potential is a ground potential and said first protective transistor is an NMOS field effect transistor having a drain electronically connected to said pad, and a source connected to said ground potential.

11. The circuit of claim 9, wherein said second protective field effect transistor is a thick field oxide field effect transistor.