Method and system for designing a circuit using RC and timing weighting of nets

• US 5,815,406 A
• Filed: 03/25/1996
• Issued: 09/29/1998
• Est. Priority Date: 03/25/1996
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Olson, Christopher Hans, Golla, Robert Thaddeus
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): Siek, Vuthe
• Application Number:
  US08/620,734
• Time in Patent Office: 918 Days
• Field of Search: 364/488-491
• US Class Current: 716/113
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A timing driven placement system and method for designing an integrated circuit. The inventive method includes the steps of identifying a plurality of nets having blocks of circuit components connected by conductive elements and assigning weights to the nets in proportion to timing and resistive-capacitive (RC) effects therein. In the preferred embodiment, the weights are used by a conventional placement program to obtain the final placements.

Claims

1. A method for designing an integrated circuit including the steps of:

identifying a plurality of nets having blocks of circuit components connected by conductive elements;

assigning weights to the plurality of nets in proportion to a combination of timing and resistive-capacitive (RC) effects therein, the step of assigning weights including the steps of;

calculating a worst case resistive-capacitive delay (Net_-- RC) of a sink pin of a net under consideration,

setting a minimum resistive-capacitive delay threshold (Min_-- RC_-- Design) associated with the pin of the net under consideration,

subtracting the minimum resistive-capacitive delay threshold (Min_-- RC_-- Design) from the worst case resistive-capacitive delay (Net_-- RC) of a sink pin of the net under consideration to acquire a first difference term (Net_-- RC-Min_-- RC_-- Design),

setting an upper limit for resistive-capacitive delay of the net (UPPER_-- RC),

subtracting the minimum resistive-capacitive delay threshold from the upper limit (UPPER_-- RC) to acquire a second difference term (UPPER_-- RC-Min_-- RC_-- Design),

dividing the first difference term by the second difference term to acquire a first ratio (Net_-- RC-Min_-- RC_-- Design)/(UPPER_-- RC-Min_-- RC_-- Design),

setting a relative percentage weight (FRAC_-- RC) to assign to RC delay values versus SLACK values representing a difference between a measured arrival time of a logical result and an expected arrival time of the result for the net under consideration,

multiplying the first ratio by the relative percentage weight (FRAC_-- RC) times 100 to acquire a first sum term,

determining a maximum or worst SLACK of the net under consideration (Net SLACK),

setting an upper limit on SLACK (UPPER_-- SLACK),

subtracting the Net SLACK from the UPPER_-- SLACK to acquire a third difference term,

determining the minimum SLACK associated with any net within the circuit (Min_-- SLACK_-- Design),

subtracting the minimum SLACK associated with any net from the UPPER_-- SLACK to acquire a fourth difference term,

dividing the third difference term by the fourth difference term to acquire a second ratio,

multiplying the second ratio by (1-FRAC_-- RC) times 100 to acquire a second sum term,

adding the first and the second sum terms, and

adding a constant to the first and the second sum terms to acquire a weight for the net; and

selecting locations for the circuit components to reduce the length of a plurality of wires therebetween in accordance with the weights, the step of selecting locations for the circuit components including the step of running a placement program using the weight for the net.

2. The method of claim 1 wherein the step of calculating a worst case RC delay of a sink pin of a net under consideration is performed with a timing tool.

3. A system for designing an integrated circuit having a plurality of nets comprising blocks of circuit components connected by conductive elements, the system including:

a processor and

a first program executed by the processor for assigning weights to the plurality of nets in proportion to a sum of timing and resistive-capacitive (RC) effects therein, the first program including instructions for;

calculating a worst case resistive-capacitive delay (Net_-- RC) of a sink pin of a net under consideration,

setting a minimum resistive-capacitive delay threshold (Min_-- RC_-- Design) associated with the pin of the net,

subtracting the minimum resistive-capacitive delay threshold (Min_-- RC_-- Design) from the worst case resistive-capacitive delay (Net_-- RC) of a sink pin of a net under consideration to acquire a first difference term (Net_-- RC-Min_-- RC_-- Design),

setting an upper limit for resistive-capacitive delay of the net (UPPER_-- RC),

subtracting the minimum resistive-capacitive delay threshold from the upper limit (UPPER_-- RC) to acquire a second difference term (UPPER_-- RC-Min_-- RC_-- Design),

dividing the first difference term by the second difference term to acquire a first ratio (Net_-- RC-Min_-- RC_-- Design)/(UPPER_-- RC-Min_-- RC_-- Design),

setting a relative percentage weight (FRAC_-- RC) to assign to RC delay values versus SLACK values representing a difference between a measured arrival time of a logical result and an expected arrival time of the result for the net under consideration,

multiplying the first ratio by the relative percentage weight (FRAC_-- RC) times 100 to acquire a first sum term,

determining a maximum or worst SLACK of the net under consideration (Net SLACK) and subtracting the Net SLACK from the UPPER_-- SLACK to acquire a third difference term,

determining the minimum SLACK associated with any net within the circuit (Min_-- SLACK_-- Design),

subtracting the minimum SLACK associated with any net from the UPPER_-- SLACK to acquire a fourth difference term,

dividing the third difference term by the fourth difference term to acquire a second ratio,

multiplying the second ratio by (1-FRAC_-- RC) times 100 to acquire a second sum term,

adding the first and the second sum terms, and

adding a constant to the first and the second sum terms to acquire a weight for the net.

4. The system of claim 3 including a second program for selecting locations for the circuit components to reduce the length of a plurality of wires therebetween in accordance with the weights.

5. A computer-readable medium containing a program for designing an integrated circuit, the program containing instructions for:

selecting a plurality of nets having blocks of circuit components and

assigning weights to the plurality of nets in proportion to a sum of timing and resistive-capacitive (RC) effects therein, the instruction for assigning weights to the plurality of nets further including the instructions for;

calculating a worst case resistive-capacitive delay (Net_-- RC) of a sink pin of a net under consideration,

setting a minimum resistive-capacitive delay threshold (Min_-- RC_-- Design) associated with the pin of the net,

subtracting the minimum resistive-capacitive delay threshold (Min_-- RC_-- Design) from the worst case resistive-capacitive delay (Net_-- RC) of a sink pin of a net under consideration to acquire a first difference term (Net_-- RC-Min_-- RC_-- Design),

setting an upper limit for resistive-capacitive delay of the net (UPPER_-- RC),

subtracting the minimum resistive-capacitive delay threshold from the upper limit (UPPER_-- RC) to acquire a second difference term (UPPER_-- RC-Min_-- RC_-- Design),

dividing the first difference term by the second difference term to acquire a first ratio (Net_-- RC-Min_-- RC_-- Design)/(UPPER_-- RC-Min_-- RC_-- Design),

setting a relative percentage weight (FRAC_-- RC) to assign to RC delay values versus SLACK values representing a difference between a measured arrival time of a logical result and an expected arrival time of the result for the net under consideration,

multiplying the first ratio by the relative percentage weight (FRAC_-- RC) times 100 to acquire a first sum term,

determining a maximum or worst SLACK of the net under consideration (Net SLACK) and subtracting the Net SLACK from the UPPER_-- SLACK to acquire a third difference term,

determining the minimum SLACK associated with any net within the circuit (Min_-- SLACK_-- Design),

subtracting the minimum SLACK associated with any net from the UPPER_-- SLACK to acquire a fourth difference term,

dividing the third difference term by the fourth difference term to acquire a second ratio,

multiplying the second ratio by (1-FRAC_-- RC) times 100 to acquire a second sum term,

adding the first and the second sum terms, and

adding a constant to the first and the second sum terms to acquire a weight for the net.