Potential generation circuit
First Claim
Patent Images
1. A potential generating circuit comprising:
- at least a first and a second diode connected MOS transistor in series connected between an output node and a given potential node and disposed in the same forward direction, each having a respective back gate always interconnected to a respective gate thereof; and
a capacitor coupled between a connection node of said first and second MOS transistors and an input node to which an alternating signal is to be applied.
1 Assignment
0 Petitions
Accused Products
Abstract
A potential generating circuit includes at least a pair of MOS transistors each of which is diode-connected and series connected between an output node and a given potential node and disposed in same forward direction. Each MOS transistor has its back gate and a gate interconnected. A capacitor is coupled between a connection node of the pair of MOS transistors and an input node to which an alternating signal is inputted.
56 Citations
8 Claims
-
1. A potential generating circuit comprising:
-
at least a first and a second diode connected MOS transistor in series connected between an output node and a given potential node and disposed in the same forward direction, each having a respective back gate always interconnected to a respective gate thereof; and a capacitor coupled between a connection node of said first and second MOS transistors and an input node to which an alternating signal is to be applied. - View Dependent Claims (2, 3, 6)
-
-
4. A DRAM comprising a substrate bearing:
-
(a) a memory cell array for storing charge, (b) row and column drivers for addressing the array to access selected cells of the array; and (c) a substrate potential generation circuit applying a prescribed potential to the substrate, comprising at least a first and a second diode-connected MOS transistor connected in series between an output node and a reference node, disposed in the same forward direction and each having a respective gate and a respective back gate always interconnected, capacitor coupled between a node interconnecting said first and second transistors and an input node. - View Dependent Claims (7)
-
-
5. A semiconductor memory device comprising:
-
(a) a memory array including a plurality of memory cells arranged in rows and columns (b) a plurality of word lines arranged corresponding to said rows and each connecting memory cells on a corresponding row; (c) a drive signal generator for generating a drive signal, comprising at least a pair of insulated gate type field effect transistors connected in series between an output node outputting said drive signal and a reference node receiving a reference voltage, disposed in the same forward direction and each having a respective gate and a respective back gate thereof always interconnected, and a capacitor coupled between a node interconnecting said pair of field effect transistors and an input node receiving an alternating signal; and (d) a word driver for transferring the drive signal received from said drive signal generator onto a word line arranged corresponding to an addressed row among said rows.
-
-
8. A potential generating circuit comprising:
-
at least first and second diode connected MOS transistors connected in series between an output node and a given potential node and disposed in the same forward direction, each having a respective back gate interconnected to a respective gate thereof; and a capacitor coupled between a connection node of said first and second MOS transistors and an input node to which an alternating signal is to be applied.
-
Specification