Power supply interface circuit providing nonvolatile storage with suitable operating and standby voltage levels

• US 5,815,455 A
• Filed: 09/19/1997
• Issued: 09/29/1998
• Est. Priority Date: 09/19/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Braithwaite, Keith Andre, Carpenter, Gary Dale, Tanner, Howard Carl, Nguyen, Cuong Thanh, Tsao, Gary Yuh, Hoang, Binh Thai
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/933,701
• Time in Patent Office: 375 Days
• Field of Search: 365/226, 365/227, 365/228, 365/229
• US Class Current: 365/229
• CPC Class Codes: G11C 5/141 Battery and back-up supplies

Abstract

A power supply interface suitable to provide voltages of appropriate magnitude to a static random access memory (SRAM) device from a combination of independent sources including a main power supply, an auxiliary power supply, and a battery. The voltages from the interface are at levels consistent with the SRAM modes of operation. During limited voltage tolerance read and write access operations, main power supply voltage is provided through a low forward voltage drop switched metal oxide field effect transistor (MOSFET). Parasitic paths, potentially producible by the transistor and affecting the battery source of power, are eliminated through the use of a second, complementary MOSFET. The second MOSFET is directly responsive to a POWERGOOD signal from the main power supply, indicating both an "on" state and an appropriate voltage level of the main power supply.

Claims

1. A power supply interface circuit, comprising:

a first input line connected to a battery of first voltage;

a second input line connected to an auxiliary supply of second voltage, the second voltage being greater than the first voltage;

a third input line connected to a main power supply of third voltage, the third voltage being nominally equal to or greater than the second voltage;

an output line connected to a nonvolatile storage device;

diode interfaces between the output line and the first input line and the second input line; and

a field effect transistor operable to selectively connect the output line to the third input line responsive to a main power supply power good signal.

2. The apparatus recited in claim 1, wherein the diodes are connected in an OR logic format.

3. The apparatus recited in claim 2, wherein the nonvolatile storage device is a static random access memory.

4. The apparatus recited in claim 1, wherein the field effect transistor is a first channel type MOSFET with an intrinsic diode connecting the output line to the third input line, and the apparatus further comprises:

a second channel type transistor, driving the first channel type transistor responsive to the power good signal.

5. The apparatus recited in claim 2, wherein the field effect transistor is a first channel type MOSFET with an intrinsic diode connecting the output line to the third input line, and the apparatus further comprises:

a second channel type transistor, driving the first channel type transistor responsive to the power good signal.

6. The apparatus recited in claim 3, wherein the field effect transistor is a first channel type MOSFET with an intrinsic diode connecting the output line to the third input line, and the apparatus further comprises:

a second channel type transistor, driving the first channel type transistor responsive to the power good signal.

7. The apparatus recited in claim 4, wherein the first channel type transistor is a p-channel device and the second channel type transistor is an n-channel device.

8. The apparatus recited in claim 5, wherein the first channel type transistor is a p-channel device and the second channel type transistor is an n-channel device.

9. The apparatus recited in claim 6, wherein the first channel type transistor is a p-channel device and the second channel type transistor is an n-channel device.

10. A data processing system with nonvolatile memory and multiple sources of power for operating the nonvolatile memory, comprising:

a computer system operable from a high output AC/DC converting main power supply;

a low output AC/DC converting auxiliary power supply operable to sustain the data in the nonvolatile memory;

a battery operable to sustain the data in the nonvolatile memory;

diode means for interconnecting the auxiliary power supply and the battery to reliably power the nonvolatile memory; and

field effect transistor means connected between the main power supply and the nonvolatile memory, operable in response to the state of a main power supply power good signal.

11. The apparatus recited in claim 10, wherein the field effect transistor means comprises a pair of field effect transistors, the first field effect transistor operable to selectively connect the main power supply to nonvolatile memory for accessing and the second field effect transistor switching responsive to the main power supply state signal.

12. The apparatus recited in claim 11, wherein the diode means comprises diodes connected in OR logic format.

13. The apparatus recited in claim 12, wherein the nonvolatile memory is static random access memory.

14. The apparatus recited in claim 13, wherein the first field effect transistor is a p-channel MOSFET device having an intrinsic diode which connects to the diodes in the OR logic format.