Synchronous semiconductor memory device and synchronous memory module
First Claim
1. A synchronous semiconductor memory device comprising:
- a first node receiving an externally applied first clock signal applied repetitively;
a first clock buffer for receiving the first clock signal to generate a first internal clock signal corresponding to the first clock signal;
input buffer means receiving an externally applied control signal and address signal in synchronization with said first internal clock signal applied from said first clock buffer to produce an internal control signal and an internal address signal for selecting a memory cell in a memory cell array including a plurality of memory cells;
a second node receiving an externally applied second clock signal, separate from said first clock signal and repetitively applied in parallel with said first clock signal;
a second clock buffer for receiving the second clock signal to produce a second internal clock signal corresponding to the second clock signal; and
output buffer means receiving and buffering internal read data read from the selected memory cell to produce and output external read data to an output node in synchronization with said second internal clock signal applied from the second clock buffer.
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Accused Products
Abstract
A first clock signal for controlling the inputting of an external signal and for controlling internal operation and a second clock signal for controlling data output are applied to separate clock input nodes, respectively. Data output timing with respect to the first clock signal can be adjusted and thus clock access time and data hold time can be adjusted. Internal data read path is pipelined to include a first transfer gate responsive to the first clock signal for transferring internal read data and a second transfer gate responsive to the second clock signal for transferring the internal read data from the first transfer gate for external outputting through an output buffer. A synchronous semiconductor memory device is provided capable of setting clock access time and data hold time at the optimal values depending on the application and of reducing the clock access time.
142 Citations
20 Claims
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1. A synchronous semiconductor memory device comprising:
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a first node receiving an externally applied first clock signal applied repetitively; a first clock buffer for receiving the first clock signal to generate a first internal clock signal corresponding to the first clock signal; input buffer means receiving an externally applied control signal and address signal in synchronization with said first internal clock signal applied from said first clock buffer to produce an internal control signal and an internal address signal for selecting a memory cell in a memory cell array including a plurality of memory cells; a second node receiving an externally applied second clock signal, separate from said first clock signal and repetitively applied in parallel with said first clock signal; a second clock buffer for receiving the second clock signal to produce a second internal clock signal corresponding to the second clock signal; and output buffer means receiving and buffering internal read data read from the selected memory cell to produce and output external read data to an output node in synchronization with said second internal clock signal applied from the second clock buffer. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11)
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12. A synchronous semiconductor memory device comprising:
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a first node for receiving an externally applied first clock signal applied repetitively; a second node for receiving an externally applied second clock signal repetitively applied in parallel with said first clock signal when the second clock signal is applied to the synchronous semiconductor memory device; input buffer circuitry receiving an externally applied control signal and address signal in synchronization with said first clock signal to produce an internal control signal and an internal address signal for selecting a memory cell in a memory cell array including a plurality of memory cells; clock selection circuitry for selecting a clock signal applied to one of the first and second nodes; and output buffer circuitry for receiving and buffering internal read data read from the selected memory cell to produce and output external read data externally in synchronization with the clock signal selected by said clock selection circuitry. - View Dependent Claims (13, 14, 15, 16)
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17. A synchronous memory module comprising:
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a plurality of synchronous semiconductor memory devices each including (a) a first pad, (b) input buffer means for incorporating a control signal and an address signal externally applied in synchronization with a clock signal externally applied to said first pad to produce an internal control signal and an internal address signal for selecting a memory cell in a memory array including a plurality of memory cells, (c) a second pad provided separately from said first pad, and (d) output means for buffering an internal read data read from the selected memory cell to produce and externally output thus produced read data in synchronization with a clock signal externally applied to said second pad; and internal clock generating means receiving a repetitively applied external clock signal for producing first and second clock signals in synchronization with the external clock signal, and for commonly applying said first clock signal to said first pad of each of said plurality of synchronous semiconductor memory devices and commonly applying said second clock signal to said second pad of each of said plurality of synchronous semiconductor memory devices. - View Dependent Claims (18, 19, 20)
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Specification