Error detector circuit for digital receiver using variable threshold based on signal quality

• US 5,815,507 A
• Filed: 04/15/1996
• Issued: 09/29/1998
• Est. Priority Date: 04/15/1996
• Status: Expired due to Term

• Current Assignee: Google Technology Holdings LLC (Alphabet Inc.)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Arora, Arvind S., Vinggaard, Niels
• Primary Examiner(s): Tu, Trinh L.
• Application Number:
  US08/632,701
• Time in Patent Office: 897 Days
• Field of Search: 371/5.1, 371/5.5, 371/20.1, 371/20.3, 371/30, 371/37.1, 371/37.4, 371/38.1, 371/39.1, 371/43, 371/44, 371/45, 371/67.1, 371/68.2, 371/5.2, 371/5.3, 371/5.4, 371/28 , 371/43.1, 371/43.6, 371/43.7, 375/224, 375/227, 375/228, 445/67.1, 445/67.3, 445/67.7, 445/135, 445/226.1, 445/226.3, 445/226.4
• US Class Current: 714/704
• CPC Class Codes: H03M 13/00 Coding, decoding or code conversion, for error detection or error correction; Coding theory basic assumptions; Coding bounds; Error probability evaluation methods; Channel models; Simulation or testing of codes error detection or error correction for analogue/digital, digital/analogue or code conversion H03M1/00 – H03M11/00; specially adapted for digital computers G06F11/08; for information storage based on relative movement between record carrier and transducer G11B, e.g. G11B20/18; for static stores G11C
• CPC Class Codes: H03M 13/35 Unequal or adaptive error protection, e.g. by providing a different level of protection according to significance of source information or by adapting the coding according to the change of transmission channel characteristics
• CPC Class Codes: H03M 13/39 Sequence estimation, i.e. using statistical methods for the reconstruction of the original codes
• CPC Class Codes: H04L 1/0054 Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/20 using signal quality detector
• CPC Class Codes: H04L 1/201 Frame classification, e.g. bad, good or erased frame indication per se H04L1/0082
• CPC Class Codes: H04L 1/208 involving signal re-encoding
• CPC Class Codes: H04L 2001/0098 Unequal error protection

Abstract

An error detector circuit (300) for a discrete receiver indicates bad frames of binary information signals which contain distorted bits of data in numbers so great as to prevent a convolutional decoder (738) from generating, accurately, a decoded signal. A variable threshold generator (440) generates a variable threshold level according to the signal quality estimate for the received signal. When bit errors are detected in numbers beyond the variable threshold or when a first preselected value of the signal quality of a received signal combined with the detected number of bit errors forms a signal beyond a second preselected value, a bad frame is indicated.

Claims

1. An error detector circuit for a receiver operative to receive a discretely-encoded signal at an input thereof, the error detector circuit operative to determine when a sequence of the discretely-encoded signal is comprised of an excessive number of signal portions of erroneous signal values, the error detector circuit comprising:

a first detector coupled to the input to determine when signal portions of the sequence of the discretely-encoded signal received by the receiver are of erroneous signal values and to generate a first error signal of a value representative of numbers of signal portions determined to be of the erroneous signal values;

a second detector coupled to the input to determine signal quality levels of the sequence of the discretely-encoded signal and to generate a signal-quality signal representative of signal quality levels determined thereat;

a combiner coupled to the first and second detectors to combine the first error signal and the signal-quality signal to form thereby a weighted error signal;

a threshold generator receiving an estimated signal quality signal and generating a variable threshold level as a function of the estimated signal quality signal; and

a signal generator coupled to the threshold generator, the first detector, and to the combiner, to generate a received-signal sequence error when either the weighted error signal is of a value beyond a preselected threshold value or the first error signal is of a value beyond the variable threshold level, wherein generation of a received-signal sequence error signal is indicative of when the sequence of the discretely-encoded signal is comprised of the excessive number of signal portions of the erroneous signal values.

2. The error detector circuit of claim 1 wherein said first detector comprises:

a soft decision signal generator to generate a soft decision signal representative of the discretely-encoded signal received by the receiver;

a decoder coupled to the soft decision signal generator to decode said soft decision signal representative of the discretely-encoded signal and to generate a decoded signal responsive to values of the soft decision signal;

a coder coupled to the decoder to re-encode the decoded signal generated by said decoder;

a hard decision converter coupled to the soft decision signal generator to convert the soft decision signal representative of the discretely-encoded signal received by the receiver into a hard decision signal; and

a comparator coupled to the hard decision converter and the coder to compare a re-encoded decoded signal generated by the coder with the hard decision signal.

3. The error detector circuit of claim 2 wherein the first error signal is of a level proportional to a magnitude of numbers of times in which values of signal portions of a sequence of the hard decision signal differ with values of a corresponding sequence of the re-encoded decoded signal generated by the coder.

4. The error detector circuit of claim 2 wherein the decoder comprises a Viterbi decoder.

5. The error detector circuit of claim 2 wherein the coder comprises a convolutional encoder.

6. The error detector circuit of claim 2 wherein said soft decision signal is comprised of a demodulated signal demodulated by the receiver.

7. The error detector circuit of claim 2 further comprising means forming a buffer for storing a sequence of signal portions of the hard decision signal formed by the hard decision converter.

8. The error detector circuit of claim 2 wherein the comparator comprises means for performing an exclusive-or logic comparison.

9. The error detector circuit of claim 1 wherein the second detector comprises a circuit to measure signal magnitude levels of at least one signal portion of a signal representative of the sequence of the discretely-encoded signal received by the receiver.

10. The error detector circuit of claim 9, wherein said second detector further comprises means for calculating weighted-average signal magnitude levels formed of a weighted average of at least two signal portions of the signal representative of the sequence of the discretely-encoded signal received by the receiver.

11. The error detector circuit as defined in claim 1, wherein the threshold generator compares a measured value of a segment of a frame to a segment threshold to determine whether the segment of the frame is bad.

12. The error detector circuit as defined in claim 11, wherein respective measured values for plurality of segments of the frame are each compared to the segment threshold, and the threshold generator selects a threshold based upon the number of segments of the frame that are determined to be bad.

13. The error detector circuit as defined in claim 12, wherein each of the segments is a burst and the measured value of each of the segments is an estimate of the noise in each burst.

14. The error detector circuit of claim 1 wherein the weighted error signal formed by said combiner is formed by multiplying values of the first error signal and the estimated signal-quality signal together.

15. The error detector circuit of claim 1 wherein said signal generator comprises a first comparator having a first input and a second input wherein the weighted error signal is applied to the first input of the first comparator and a first threshold signal of a value corresponding to the preselected threshold value is applied to the second input of the first comparator, said first comparator being operative to generate a first comparison signal responsive to times in which the weighted error signal is of a value greater than the first threshold signal.

16. The error detector circuit of claim 15 wherein said signal generator further comprises a second comparator having a first input and a second input wherein the first error signal is applied to the first input of the second comparator and the variable threshold level is applied to the second input of the second comparator, said second comparator being operative to generate a second comparison signal responsive to times in which the first error signal is of a value greater than the variable threshold level.

17. The error detector circuit of claim 16 wherein said signal generator further comprises a logical-OR gate having a first input and a second input wherein the first comparison signal is applied to the first input of the logical-OR gate and wherein the second comparison signal is applied to the second input of the logical-OR gate, said logical-OR gate being operative to generate an output signal forming a received-signal sequence error signal when either the first comparison signal or the second comparison signal is applied thereto.

18. The error detector circuit as defined in claim 1, further including a signal quality estimate generator generating an estimate of a signal quality in a received signal from a noise signal, the estimate of the signal quality input to the threshold generator as the estimated signal quality signal.

19. A bad frame indicator for a digital receiver, comprising:

a first circuit for generating a first error signal of a value representative of a number of erroneous signal values in a frame input to the digital receiver;

a second circuit generating respective estimated signal quality signals representative of signal quality of each of a plurality of segments of the frame input to the digital receiver;

a threshold generator coupled to the second circuit to derive a variable threshold as a function of a number of the segments of the frame that are determined to be bad based upon the respective estimated signal quality signal for each segment; and

a signal generator coupled to the threshold generator and the first circuit for generating a received-signal sequence error signal when the first error signal is of a value beyond the variable threshold, wherein generation of the received-signal sequence error signal is indicative of when the frame input to the digital receiver is comprised of an excessive number of signal portions of erroneous signal values.

20. In a radiotelephone transceiver having digital receiver circuitry operative to receive discretely-encoded signals, a combination with the digital receiver circuitry of an error detector circuit for determining when a sequence of the discretely-encoded signals is comprised of an excessive number of signal portions of erroneous signal values, said error detector circuit comprising:

a first generator generating a first error signal of a value representative of a number of erroneous signal values in the sequence of discretely encoded signals;

a generator generating a signal-quality signal representative of signal quality levels of signals input to the digital receiver circuitry;

a circuit to combine the first error signal and the signal-quality signal to form a weighted error signal;

a signal quality estimate generating circuit to generate an estimate of signal quality level in the signals input to the digital receiver circuitry;

an error quality circuit coupled to the signal quality estimate generating circuit to generate a variable threshold as a function of the estimate of signal quality level; and

a signal generator coupled to the first generator, to the quality circuit and to the error circuit to generate a received-signal sequence error when either the weighted error signal is of a value beyond a first preselected value or the first error signal is of a value beyond the variable threshold, wherein generation of the received-signal sequence error is indicative of when the sequence of the discretely-encoded signals is comprised of the excessive number of signal portions of erroneous signal values.