Integrated network switching hub and bus structure

• US 5,815,681 A
• Filed: 05/21/1996
• Issued: 09/29/1998
• Est. Priority Date: 05/21/1996
• Status: Expired due to Fees

• Current Assignee: PDACO LIMITED
• Original Assignee: Elonex PLC (Elonex Uk Ltd.)
• Inventors: Kikinis, Dan
• Primary Examiner(s): AUVE, GLENN ALLEN
• Application Number:
  US08/651,118
• Time in Patent Office: 861 Days
• Field of Search: 395/311, 395/309, 395/310, 395/200.02, 395/200.2, 395/293, 395/200.8, 395/200.68, 395/200.53, 395/200.55
• US Class Current: 710/316
• CPC Class Codes: H04L 49/254 Centralised controller, i.e. arbitration or scheduling
• CPC Class Codes: H04L 49/3027 Output queuing
• CPC Class Codes: H04L 49/351 for local area network [LAN], e.g. Ethernet switches

Abstract

A network switching hub is implemented on an IC chip, and has a bus connected to external ports through sets of que switch transistors, source to drain for data switched onto the bus, the queue switch transistors gated simultaneously by control lines from an on-board arbitrator controller following a preprogrammed arbitration scheme. Data is switched off the bus and hub by port adapter controllers connected to read amplifier receivers connected directly to the on-chip bus, the port adapter controllers enabled by the arbitrator controller following the same preprogrammed arbitration scheme. Ports may be serial or parallel, and may be adapted to special purposes, such as PCI and hub to hub connection for expansion.

Claims

1. An integrated circuit (IC) switching hub, comprising:

a parallel bus of n bus lines implemented as traces on the IC;

a first data port adapter controller connected by n first port lines through a first output buffer to the bus, each first port line connected to a bus line source-to-drain through one of a set of first queue switch transistors, and connected to a first data port providing a first external data link for the switching hub;

a first read amplifier connected by n first receiver lines one each directly to each one of the n bus lines, and by a first data link to the first port adapter controller;

a second data port adapter controller connected by n second port lines through a second output buffer to the bus, each second port line connected to a bus line source-to-drain through one of a set of second queue switch transistors, and connected to a second data port providing a second external data link for the switching hub;

a second read amplifier connected by n second receiver lines one each directly to each one of the n bus lines and by a second data link to the second port adapter controller; and

an arbitrator controller connected by a first control line to the gates of the first set of queue switch transistors, by a second control line to the gates of the second set of queue switch transistors, by a third control line to the first port adapter controller, and by a fourth control line to the second port adapter controller;

wherein the arbitrator controller is adapted to switch data from the first and second port adapter controllers onto the bus through the first and second output buffers and the first and second sets of queue switch transistors by switching the gates of the transistors via the first and second control lines respectively, and adapted to transfer data from the bus to the first and second external data links via the first and second read amplifiers through the first and second port adapter controllers by enabling the respective port adapter controllers via the third and fourth control lines respectively, according to a preprogrammed arbitration scheme.

2. An IC switching hub as in claim 1 wherein the ports are serial ports adapted for network communication.

3. An IC switching hub as in claim 1 further comprising plural pairs of external data ports wherein one of the external data ports is adapted for connecting the IC switching hub to a second IC switching hub.

4. An IC switching hub as in claim 1 wherein the queue switch transistors are implemented in one layer on the chip, and connections are implemented in another layer.

5. An integrated circuit (IC) switching hub, comprising:

a parallel bus of n bus lines implemented as traces on the IC;

a first data port adapter controller connected by n first port lines through a first output buffer to the bus, each first port line connected to a bus line source-to-drain through one of a set of first queue switch transistors, and connected to a first data port providing a first external data link for the switching hub;

a second data port adapter controller connected by n second port lines through a second output buffer to the bus, each second port line connected to a bus line source-to-drain through one of a set of second queue switch transistors, and connected to a second data port providing a second external data link for the switching hub;

a read amplifier connected by n receiver lines one each directly to each one of the n bus lines and by a data link to the first and second port adapter controllers; and

an arbitrator controller connected by a first control line to the gates of the first set of queue switch transistors, by a second control line to the gates of the second set of queue switch transistors, by a third control line to the first port adapter controller, and by a fourth control line to the second port adapter controller;

wherein the arbitrator controller is adapted to switch data from the first and second port adapter controllers onto the bus through the first and second output buffers and the first and second sets of queue switch transistors by switching the gates of the transistors via the first and second control lines respectively, and adapted to transfer data from the bus to the first and second external data links via the read amplifier through the first and second port adapter controllers by enabling the respective port adapter controllers via the third and fourth control lines respectively, according to a preprogrammed arbitration scheme.

6. An IC switching hub as in claim 5 further comprising plural additional sets of ports in pairs, each pair of ports sharing an additional read amplifier connected to both port adapter controllers of each pair.

7. An IC switching hub as in claim 6 wherein one port is a PCI parallel port adapted for communication with a PCI bus.