Method and apparatus for optimizing complex control structures using abstract web patterns

• US 5,815,721 A
• Filed: 04/25/1996
• Issued: 09/29/1998
• Est. Priority Date: 04/25/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Benitez, Manuel E.
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): Nguyen, Cuong H.
• Application Number:
  US08/637,988
• Time in Patent Office: 887 Days
• Field of Search: 364/280.4, 364/280.5, 364/280, 364/973, 364/262.4, 364/247, 295/705, 295/708, 295/709, 295/707, 295/680, 295/684, 295/703
• US Class Current: 717/160
• CPC Class Codes: G06F 8/443 Optimisation

Abstract

An optimizing compiler for optimizing a computer program. The compiler builds abstract web representations for the code segments of the computer program. The compiler also maintains a library of abstract web patterns. Each abstract pattern in the library represents an optimized sequence of computer instructions. The compiler compares each abstract web generated from the code segments with the abstract web patterns in its library. If any of the abstract webs match, the compiler replaces the original code segment in the computer program with the optimized sequence of instructions corresponding to the matching abstract web pattern. By using the above described technique, the compiler can replace loops with instructions that implicitly iterate. In addition, the compiler can micro-vectorize code segments and remove unnecessary instructions from loops.

Claims

1. A method of optimizing a selected program segment of a computer program, comprising the steps of:

generating a first abstract representation of the selected program segment;

comparing the first abstract representation with at least one other abstract representation stored in a memory of a computer system to determine if a match exists between the generated abstract representation and at least one other stored abstract representation, wherein each other abstract representation is associated with an optimized instruction sequence; and

replacing the selected program segment with the optimized instruction sequence associated with a matched one of the at least one stored abstract representation.

2. The method of claim 1, wherein the generated and matched abstract representations are webs.

3. The method of claim 1, wherein the program sequence removes at least one instruction from within a loop.

4. The method of claim 3, wherein the optimized instruction segment moves instructions outside the loop.

5. The method of claim 1, wherein the optimized instruction sequence comprises at least one micro-vectorized instruction.

6. The method of claim 1, wherein the computer system comprises a 64-bit architecture.

7. An compiler adapted for execution on a computer system having a CPU and a memory, comprising:

means, executing on the CPU and stored in the memory, for converting a high-level computer program into low-level code comprised of at least one code segment;

means for scanning the low-level code and generating a first abstract representation of the code segment;

means for comparing the first abstract representation with at least one other abstract representation stored in the memory, wherein the compared at least one other abstract representation has an associated optimized code segment; and

means for replacing the code segment with the optimized code segment corresponding to a matched one in the memory of the at least one other abstract representation.

8. The compiler of claim 7, wherein the first and at least one other abstract representations are webs.

9. The compiler of claim 7, wherein the code segment is a loop.

10. The compiler of claim 9, wherein the optimized code segment removes at least one instruction from within the loop.

11. The compiler of claim 7, wherein the optimized code segment comprises at least one micro-vectorized instruction.

12. The compiler of claim 7, wherein the computer system comprises a 64-bit architecture.

13. The compiler of claim 7, wherein the computer system comprises a RISC architecture.

14. A computer program product having a computer readable medium having computer program logic recorded thereon for optimizing code segments on a computer system having a processor and a memory, the computer program product comprising:

means, executing on the processor, for building a first abstract representation of a code segment;

means for comparing the first abstract representation with a second abstract representation stored in the memory, wherein the second abstract representation represents an optimized code segment;

means for replacing the code segment with the optimized code segment if the first and second abstract representations match.

15. The computer program product of claim 14, wherein the first and second abstract representations are webs.

16. The computer program product of claim 14, wherein the code segment is a loop.

17. The computer program product of claim 16, wherein the optimized code segment removes at least one instruction from within the loop.

18. The computer program product of claim 14, wherein the optimized code segment comprises at least one micro-vectorized instruction.

19. The computer program product of claim 14, wherein the second abstract representation is one of a plurality of abstract representations stored in the memory.