Data transferring device and video game apparatus using the same
First Claim
1. A data transferring device, which is connected to a plurality of data transmitting and receiving devices via corresponding external buses, for transferring data between the plurality of the data transmitting and receiving devices comprising:
- a plurality of bus interface circuits, to which each of the corresponding external buses is connected; and
a direct memory access circuits operatively connected to the plurality of bus interface circuits by an internal bus for transferring the data between the plurality of bus interface circuits.
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Accused Products
Abstract
A data transferring device transfers data via data buses between a plurality of data transmitting and receiving devices, and can continuously transfer data read out from a memory. The data transferring device includes a DMA (Dynamic Memory Access), which writes readable data in the memory per a plurality of bytes from a byte boundary. The data transferring device has the advantageous to be applied to a video game apparatus. The data transferring device has a basic structure having a plurality of data transmitting and receiving devices, a plurality of bus interface circuits connected via buses corresponding to each of the plurality of the data transmitting and receiving devices a direct memory access circuit (DMA), which transfers the data transmitted to one bus interface circuit to another bus interface circuit. Further, the plurality of bus interface circuits divide and unite data in correspondence with size of the connected buses to transfer the data to another bus interface circuit.
72 Citations
14 Claims
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1. A data transferring device, which is connected to a plurality of data transmitting and receiving devices via corresponding external buses, for transferring data between the plurality of the data transmitting and receiving devices comprising:
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a plurality of bus interface circuits, to which each of the corresponding external buses is connected; and a direct memory access circuits operatively connected to the plurality of bus interface circuits by an internal bus for transferring the data between the plurality of bus interface circuits. - View Dependent Claims (2, 3, 4)
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5. An information processing apparatus, comprising:
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a data transferring device, which is connected to a plurality of data transmitting and receiving devices via corresponding external buses, for transferring data between the plurality of the data transmitting and receiving devices, said data transferring device including a plurality of bus interface circuits, to which each of the corresponding external buses is connected, wherein at least two of the plurality of bus interface circuits are respectively connected to external buses, each having a different bus size from that of the other, and a direct memory access circuit, operatively connected to the plurality of bus interface circuits by an internal bus, for transferring the data between the plurality of bus interface circuits, and wherein at least one of the plurality of the bus interface circuits is connected with a data transmitting and receiving device via an external bus from the outside of the information processing apparatus, and the bus size of the external bus connected to the data transmitting and receiving device has the minimum size within the external buses connected to the data transferring device.
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6. A data transferring device connected to a first external bus and a second external bus having 1/n (n means positive integer) of the bus size of the first external bus, comprising:
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first and second bus interface circuits, to which the first and second external buses are respectively connected; a direct memory access circuit for transferring data on the first external bus, which are transmitted to the first bus interface circuit, to the second bus interface circuit; and an internal bus connected to the first and second bus interface circuits and the direct memory access circuit, having the same bus size as that of the first external bus, the first bus interface circuit converting the data, which are continuously transmitted with a predetermined period synchronized with a clock signal, on the first external bus to the data having 1/n of the predetermined period and outputting the converted data to the internal bus, the direct memory access circuit shifting the data by a 1/n period and re-transmitting the shifted data to the internal bus, and the second bus interface circuit taking the data of 1/n of the predetermined period, which are re-transmitted from the direct memory access circuit to the internal bus, making the taken data to a continuous data sequence with the 1/n period, and re-transmitting the continuous data sequence with the 1/n period to the second external bus. - View Dependent Claims (7, 8, 9)
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10. A video game apparatus comprising:
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a CPU for executing a game program; a first video display processor for controlling displayed models or sprites on a picture plane; a second video display processor for controlling a scroll of the picture plane and determining priority of displayed pictures; and a system control unit connected to the CPU, each of the first and second video display processors, through corresponding external buses, including, a first bus interface circuit, to which the CPU is connected, a second bus interface circuit, to which the first and second video display processors are connected, and a direct memory access circuit for transferring data, which are transmitted to the first bus interface circuit, to the second bus interface circuit. - View Dependent Claims (11)
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12. A direct memory access circuit, which reads in and transfers data per a plurality of n bytes, comprising:
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a first latch circuit for latching n bytes of data, which are read in; a second latch circuit operatively connected to the first latch circuit for latching (n-1) bytes of the data output from the first latch circuit; and a selector supplied with the n bytes of data latched in the first latch circuit and combined n bytes, which are formed by combining the latched n byte data of the first latch circuit with the latched (n-1) byte data of the second latch circuit and shifting sequentially by one byte, for selecting a desired set of n bytes of data from the supplied n bytes. - View Dependent Claims (13, 14)
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Specification