LOC SIMM and method of fabrication

• US 5,817,535 A
• Filed: 03/05/1997
• Issued: 10/06/1998
• Est. Priority Date: 06/25/1996
• Status: Expired due to Term

• Current Assignee: Micron Technology, Inc.
• Original Assignee: Micron Technology, Inc.
• Inventors: Akram, Salman
• Primary Examiner(s): Tsai, Jey
• Assistant Examiner(s): ZARNEKE, DAVID A
• Application Number:
  US08/811,935
• Time in Patent Office: 580 Days
• Field of Search: 438/15, 438/14
• US Class Current: 438/15
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/06136 Covering only the central area of the surface to be connected, i.e. central arrangements
• CPC Class Codes: H01L 2224/32225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45124 Aluminium (Al) as principal constituent
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/4824 Connecting between the body and an opposite side of the item with respect to the body
• CPC Class Codes: H01L 2224/48247 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/49175 Parallel arrangements
• CPC Class Codes: H01L 2224/73265 Layer and wire connectors
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/4951 Chip-on-leads or leads-on-chip techniques, i.e. inner lead fingers being used as die pad
• CPC Class Codes: H01L 23/538 the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates H05K takes precedence; manufacture or treatment H01L21/4846 ; mountings per se H01L23/12; materials H01L23/49866
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 24/49 of a plurality of wire connectors
• CPC Class Codes: H01L 24/73 Means for bonding being of different types provided for in two or more of groups H01L24/10, H01L24/18, H01L24/26, H01L24/34, H01L24/42, H01L24/50, H01L24/63, H01L24/71
• CPC Class Codes: H01L 25/0655 : the devices being arranged next to each other
• CPC Class Codes: H01L 2924/00 : Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 : Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/00015 : the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed as prior art
• CPC Class Codes: H01L 2924/01079 : Gold [Au]
• CPC Class Codes: H01L 2924/01087 : Francium [Fr]
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/207 : Diameter ranges
• CPC Class Codes: H01L 2924/30107 : Inductance

Abstract

A lead-over-chip single-in-line memory module (LOC SIMM) and method of manufacturing is disclosed that provides for shortened wire bonds and ease of rework for unacceptable semiconductor dice. More specifically, the LOC SIMM of the present invention includes a plurality of slots extending through a circuit board with an equal number of semiconductor dice attached thereto such that the active surfaces of the dice are exposed through the slots. Wire bonds or TAB connections are made from the exposed active surface of the die, through the slot, and to contacts on the top surface of the circuit board. Dice proven unacceptable during burn-in and electrical testing of the module are replaced by known good dice (KGD) by breaking their respective wire bonds, attaching a KGD to the circuit board, and forming new electrical connections between the KGD and the circuit board.

Claims

1. A method of manufacturing a multi-chip module, comprising:

providing a carrier substrate having a top surface and a bottom surface, a plurality of openings;

a plurality of recesses partially extending into said bottom side, each aligned with one of said plurality of openings;

therethrough, at least one recess partially extending into said carrier substrate from said bottom surface and aligned with one of said plurality of openings, and a plurality of conductive traces on said top surface proximate each of said plurality of openings;

attaching a plurality of semiconductor dice each having an active surface with a plurality of bond pads disposed thereover adjacent said bottom surface of said carrier substrate such that a portion of an active surface of each of said plurality of semiconductor dice is aligned with one of said plurality of recesses openings and said plurality of bond pads is exposed therethrough, at least one of said plurality of semiconductor dice being secured at least partially within said at least one recess; and

electrically connecting at least one of said plurality of conductive traces to at least one of said plurality of bond pads of each of said plurality of semiconductor dice through an intermediate conductive element to form a circuit including said conductive traces.

2. The method of claim 1, further including testing said plurality of semiconductor dice after electrical connection thereof to said conductive traces and identifying at least one defective die.

3. The method of claim 2, further including replacing said at least one defective die with a known good die in said circuit without physically removing said at least one defective die from said carrier substrate.

4. The method of claim 3, further including opening conductive paths defined by said at least one intermediate conductive element connected between said at least one bond pad of said defective die and said at least one of said conductive traces, attaching said replacement known good die to said top surface over said at least one opening corresponding to said at least one defective die, and electrically connecting said known good die to at least some of said conductive traces of said carrier substrate.

5. The method of claim 4, wherein said known good die is back-side attached to said top surface, and is electrically connected to said conductive traces through intermediate conductive elements.

6. The method of claim 5, wherein said intermediate conductive elements are selected from the group comprising wire bonds and TAB conductors.

7. The method of claim 4, wherein said known good die is attached to said top surface in active surface facing relationship thereto, and is electrically connected to said conductive traces by conductive protrusions extending transversely from said active surface to said conductive traces.

8. The method of claim 1, further including forming a wall around at least a portion of a perimeter of said top surface of said carrier substrate.

9. The method of claim 8, further including attaching a lid to said wall.

10. The method of claim 1, further including forming a wall around at least a portion of a perimeter of said bottom surface of said carrier substrate.

11. The method of claim 10, further including attaching a lid to said wall.

12. The method of claim 1, further including encapsulating said plurality of semiconductor dice.

13. The method of claim 12, wherein said encapsulating includes forming at least one glob top thereover.

14. The method of claim 1, further including forming at least some of said conductive traces on said top surface of a length and orientation to extend away from openings to which said traces are proximate a sufficient distance to permit placement of a die over each of said proximate openings which is functionally equivalent to a die under the same proximate opening and adjacent said bottom surface with sufficient clearance from a perimeter of each die so placed to electrically connect to said extended traces through intermediate conductive elements.

15. A method of fabricating a multi-chip module, comprising:

a carrier substrate, having a top and a bottom side with a plurality of openings therethrough, a plurality of semiconductor dice, each having an active surface including a plurality of bond pads thereon, attached to said bottom side with said plurality of bond pads of said plurality of semiconductor dice exposed through said plurality of openings, electrically connected, via a plurality of wire bonds, to conductors carried on said top side proximate each of said plurality of openings extending over at least a portion of each of said plurality of semiconductor dice,

testing said semiconductor dice after attachment and connection to said substrate and establishing the presence of at least one bad die on said substrate; and

attaching a known good die to said substrate and electrically connecting said known good die to said substrate in place of said at least one bad die without detaching said at least one bad die from said substrate.

16. The method of claim 15, further comprising superimposing said known good die over said at least one bad die and on an opposite side of said carrier substrate therefrom.