Method for formation of thin film transistors on plastic substrates

• US 5,817,550 A
• Filed: 03/05/1996
• Issued: 10/06/1998
• Est. Priority Date: 03/05/1996
• Status: Expired due to Term

• Current Assignee: Lawrence Livermore National Security LLC (Government of the United States of America)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: Carey, Paul G., Smith, Patrick M., Sigmon, Thomas W., Aceves, Randy C.
• Primary Examiner(s): Bowers, Jr., Charles L.
• Assistant Examiner(s): Radomsky, Leon
• Application Number:
  US08/611,318
• Time in Patent Office: 945 Days
• Field of Search: 437/19, 437/21, 437/40 TFT, 437/40 TFI, 437/41 TFT, 437/41 TFI, 437/173, 437/174, 437/907, 437/908, 148/DIG. 90-DIG. 93, 257/66, 257/70, 438/166, 438/308, 438/487, 438/535
• US Class Current: 438/166
• CPC Class Codes: H01L 21/02422 Non-crystalline insulating materials, e.g. glass, polymers
• CPC Class Codes: H01L 21/02488 Insulating materials
• CPC Class Codes: H01L 21/02532 Silicon, silicon germanium, germanium
• CPC Class Codes: H01L 21/02686 Pulsed laser beam
• CPC Class Codes: H01L 21/268 using electromagnetic radiation, e.g. laser radiation
• CPC Class Codes: H01L 27/1214 comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
• CPC Class Codes: H01L 27/1285 using control of the annealing or irradiation parameters, e.g. using different scanning direction or intensity for different transistors
• CPC Class Codes: H01L 29/66757 Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
• CPC Class Codes: H01L 29/78603 characterised by the insulating substrate or support H01L29/78657 takes precedence
• CPC Class Codes: H01L 29/78666 with normal-type structure, e.g. with top gate
• CPC Class Codes: H01L 29/78675 with normal-type structure, e.g. with top gate

Abstract

A process for formation of thin film transistors (TFTs) on plastic substrates replaces standard thin film transistor fabrication techniques, and uses sufficiently lower processing temperatures so that inexpensive plastic substrates may be used in place of standard glass, quartz, and silicon wafer-based substrates. The process relies on techniques for depositing semiconductors, dielectrics, and metals at low temperatures; crystallizing and doping semiconductor layers in the TFT with a pulsed energy source; and creating top-gate self-aligned as well as back-gate TFT structures. The process enables the fabrication of amorphous and polycrystalline channel silicon TFTs at temperatures sufficiently low to prevent damage to plastic substrates. The process has use in large area low cost electronics, such as flat panel displays and portable electronics.

Claims

1. A method for fabricating silicon thin film transistors on a low-temperature plastic substrate, comprising:

providing a low temperature plastic substrate,

forming a first insulating layer on the substrate,

forming a layer of amorphous silicon on the first insulating layer,

forming a second insulating layer on the amorphous silicon layer,

forming a metal layer on the second insulating layer,

removing a portion of the metal layer,

removing a portion of the second insulating layer so as to leave at least a portion of the silicon layer exposed,

doping and crystallizing the exposed silicon layer by pulsed laser processing,

providing a third insulating layer on the doped silicon layer and a remaining portion of the metal layer,

forming contact vias in the third insulating layer, and

forming source, gate, and drain contact and interconnect metalization in the vias.

2. The method of claim 1, additionally including converting at least a portion of the amorphous silicon layer to poly-silicon prior to forming the second insulating layer.

3. The method of claim 2, wherein converting the amorphous silicon to poly-silicon is carried out by directing at least one laser pulse onto at least a portion of the amorphous silicon layer.

4. The method of claim 3, wherein at least one laser pulse is produced by an excimer laser.

5. The method of claim 1, wherein the first and second insulating layers are formed of SiO₂, SiN, or polyamide.

6. The method of claim 1, wherein the gate metal layer is formed of Al, Cu, Mo, Cr, Ta, W, Ni, Ti, Si, Ti--Si, Al--Si, Al--Cu, Ti--Al, and silicides.

7. The method of claim 1, wherein the source, gate, and drain interconnect metalization are formed of Al, Cu, Mo, Cr, Ta, W, Ni, Ti, Ti--Si, Al--Si, Al--Cu, Ti--Al, and silicides.

8. The method of claim 1, wherein the doping of the exposed silicon is carried out in a dopant gas selected from the group consisting of PF₅, BF₃, B₂ H₆, and AsF₅.

9. The method of claim 1, wherein the doping is carried out using a predeposited dopant film by a technique selected from the group of ion shower, ion implantion, and CVD deposition.

10. The method of claim 1, wherein the crystallizing of the exposed silicon is carried out by directing laser pulses thereonto with increasing laser fluences for each of the laser pulses or each group of multiple laser pulses.

11. The method of claim 10, wherein the laser fluences are in a range of 30-600 mJ/cm².

12. The method of claim 1, wherein doping and/or crystallization of the exposed silicon is carried out under vacuum conditions.

13. The method of claim 1, additionally including forming the low-temperature plastic substrate from material selected from the group consisting of PET, E-CTFE, E-TFE, PES, PTFE, FEP, and HDPE.

14. The method of claim 1, wherein the low temperature plastic substrate is composed of material incapable of withstanding sustained process temperatures of greater than about 250°

C.

15. The method of claim 1, wherein forming the first and second insulating layers and the amorphous silicon layer is carried out using a temperature of not greater than about 100°

C.

16. The method of claim 1, additionally including subjecting the low-temperature plastic substrate to an annealing temperature of about 110°

to 150°

C. prior to forming the first insulating layer thereon.