Method for making improved polysilicon FET gate electrode structures and sidewall spacers for more reliable self-aligned contacts (SAC)

• US 5,817,562 A
• Filed: 01/24/1997
• Issued: 10/06/1998
• Est. Priority Date: 01/24/1997
• Status: Expired due to Term

• Current Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Original Assignee: Taiwan Semiconductor Manufacturing Company Limited
• Inventors: Chang, Tzong-Sheng, Tsao, Jenn, Chou, Chen-Cheng
• Primary Examiner(s): CHAUDHARI, CHANDRA P
• Application Number:
  US08/789,212
• Time in Patent Office: 620 Days
• Field of Search: 438/305, 438/306, 438/307, 438/586, 438/595
• US Class Current: 438/305
• CPC Class Codes: H01L 21/76897 Formation of self-aligned vias or contact plugs, i.e. involving a lithographically uncritical step self-aligned silicidation on field effect transistors H01L29/665

Abstract

A method was achieved for making FET stacked gate electrode structures with improved sidewall profiles. These more vertical sidewalls improve the control tolerance of the gate electrode length (L_eff) and improve the shape of the sidewall spacers for making more reliable metal contacts to the self-aligned source/drain contact areas. The method uses a stacked gate electrode layer having a TEOS oxide and a hard mask of silicon nitride on the gate electrode polysilicon layer. During patterning of the stacked gate electrode structure using a photoresist mask, the hard mask minimizes the buildup of a polymer on the TEOS oxide sidewall. This polymer would otherwise act as a masking material resulting in an abrupt step at the TEOS oxide/polysilicon interface when the polysilicon etch is completed. This results in improved gate electrode line length tolerance and much improved sidewall spacers that minimize electrical shorts between the metal source/drain contacts and the polysilicon gate electrodes.

Claims

1. A method for making improved gate electrodes and sidewall spacers for field effect transistors (FETs) having self-aligned contacts (SAC) comprising the steps of:

providing a semiconductor substrate having device areas;

forming a gate oxide on said device areas;

depositing a polysilicon layer on said device areas and elsewhere on said substrate, said polysilicon layer being conductively doped;

depositing a first insulating layer on said polysilicon layer;

depositing a hard mask layer on said first insulating layer;

patterning by using a photoresist mask and anisotropic plasma etching said hard mask, said first insulating layer, and said first polysilicon layer, thereby forming stacked gate electrode structures having vertical sidewalls over said device areas;

forming by ion implantation lightly doped source/drain areas in said device areas adjacent to said gate electrode structures;

growing by thermal oxidation a polysilicon oxide layer on sidewalls of said polysilicon layer in said stacked gate electrode structures and concurrently on said lightly doped source/drain areas;

depositing a conformal first silicon nitride layer over said stacked gate electrode structures;

depositing a conformal second insulating layer on said first silicon nitride layer;

anisotropically plasma etching said second insulating layer and said first silicon nitride layer thereby forming insulating sidewall spacers on said sidewalls of said stacked gate electrode structures wherein said first silicon nitride layer remaining in said sidewall spacers is contiguous with said hard mask layer;

forming source/drain contact areas in said device areas adjacent to said insulating sidewall spacers by ion implanting into said substrate;

depositing a blanket conformal second silicon nitride layer;

depositing a third insulating layer and annealing to form an essentially planar surface;

photoresist masking and selectively wet etching in said third insulating layer to said second silicon nitride layer to form openings extending partially over said stacked gate electrode structures, thereby forming self-aligned source/drain contact openings over said source/drain contact areas;

plasma etching said second silicon nitride layer in said source/drain contact openings to said polysilicon oxide layer formed on said source/drain contact areas;

performing a pre-metal wet-etch dip to remove said polysilicon oxide thereby exposing said source/drain contact areas;

depositing and patterning a metal layer to form electrical contacts to said source/drain contact areas thereby completing said field effect transistors.

2. The method of claim 1, wherein said semiconductor substrate is a heavily doped single-crystal silicon having a lightly doped epitaxial layer thereon.

3. The method of claim 1, wherein said polysilicon layer is between about 2000 and 3500 Angstroms thick.

4. The method of claim 1, wherein said polysilicon layer is conductively doped having a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm³.

5. The method of claim 1, wherein said first insulating layer is composed of silicon oxide (SiO₂) and is deposited by chemical vapor deposition (CVD) using a reactant gas of tetraethosiloxane (TEOS).

6. The method of claim 1, wherein said first insulating layer is between about 540 and 660 Angstroms thick.

7. The method of claim 1, wherein said hard mask layer is composed of silicon nitride (Si₃ N₄) and has a thickness of between about 1350 and 1650 Angstroms.

8. The method of claim 1, wherein said hard mask minimizes the polymer buildup on said first insulating layer sidewalls thereby resulting in said vertical sidewalls for said gate electrode structures to improve the tolerance of polysilicon gate electrode lengths.

9. The method of claim 1, wherein said polysilicon oxide layer is grown to a thickness of between about 80 and 100 Angstroms.

10. The method of claim 1, wherein said first silicon nitride layer is deposited to a thickness of between about 270 and 330 Angstroms.

11. The method of claim 1, wherein said second insulating layer is deposited by chemical vapor deposition using reactant gas tetraethosiloxane (TEOS).

12. The method of claim 1, wherein said second silicon nitride layer has a thickness of between about 270 and 330 Angstroms.

13. The method of claim 1, wherein said third insulating layer is composed of borophosphosilicate glass (BPSG) having a thickness of between about 2700 and 3300 Angstroms.

14. A method for making improved gate electrodes and sidewall spacers for field effect transistors (FETS) having self-aligned contacts (SAC) comprising the steps of:

providing a semiconductor substrate having device areas;

forming a gate oxide on said device areas;

depositing a polysilicon layer on said device areas and elsewhere on said substrate, said polysilicon layer being conductively doped;

depositing on said polysilicon layer a first insulating layer composed of a silicon oxide deposited by chemical vapor deposition (CVD) using reactant gas tetraethosiloxane (TEOS);

depositing a hard mask layer composed of silicon nitride on said first insulating layer;

patterning by using a photoresist mask and anisotropic plasma etching said hard mask, said first insulating layer, and said polysilicon layer, thereby forming stacked gate electrode structures having vertical sidewalls over said device areas;

forming by ion implantation lightly doped source/drain areas in said device areas adjacent to said gate electrode structures;

growing by thermal oxidation a polysilicon oxide layer on sidewalls of said polysilicon layer in said stacked gate electrode structures and concurrently on said lightly doped source/drain areas;

depositing a conformal first silicon nitride layer over said stacked gate electrode structures;

depositing a conformal second insulating layer on said first silicon nitride layer;

anisotropically plasma etching said second insulating layer and said first silicon nitride layer thereby forming insulating sidewall spacers on said sidewalls of said stacked gate electrode structures wherein said first silicon nitride layer remaining in said sidewall spacers is contiguous with said hard mask layer;

forming source/drain contact areas in said device areas adjacent to said insulating sidewall spacers by ion implanting into said substrate;

depositing a blanket conformal second silicon nitride layer;

depositing a third insulating layer and annealing to form an essentially planar surface;

photoresist masking and selectively wet etching in said third insulating layer to said second silicon nitride layer to form openings extending partially over said stacked gate electrode structures, thereby forming self-aligned source/drain contact openings over said source/drain contact areas;

plasma etching said second silicon nitride layer in said source/drain contact openings to said polysilicon oxide layer formed on said source/drain contact areas;

performing a pre-metal wet-etch dip to remove said polysilicon oxide thereby exposing said source/drain contact areas;

depositing and patterning a metal layer to form electrical contacts to said source/drain contact areas thereby completing said field effect transistors.

15. The method of claim 14, wherein said semiconductor substrate is a heavily doped single-crystal silicon having a lightly doped epitaxial layer thereon.

16. The method of claim 14, wherein said polysilicon layer is between about 2000 and 3500 Angstroms thick.

17. The method of claim 14, wherein said polysilicon layer is conductively doped having a concentration of between about 1.0 E 19 and 1.0 E 21 atoms/cm³.

18. The method of claim 14 wherein said first insulating layer is between about 540 and 660 Angstroms thick.

19. The method of claim 14, wherein said hard mask minimizes the polymer buildup on said first insulating layer sidewalls thereby resulting in said vertical sidewalls for said gate electrode structures to improve the tolerance of polysilicon gate electrode lengths.

20. The method of claim 14, wherein said polysilicon oxide layer is grown to a thickness of between about 80 and 100 Angstroms.

21. The method of claim 14, wherein said first silicon nitride layer is deposited to a thickness of between about 270 and 330 Angstroms.

22. The method of claim 14, wherein said second insulating layer is deposited by chemical vapor deposition using reactant gas tetraethosiloxane (TEOS).

23. The method of claim 14, wherein said second silicon nitride layer has a thickness of between about 270 and 330 Angstroms.

24. The method of claim 14 wherein said third insulating layer is composed of borophosphosilicate glass (BPSG) having a thickness of between about 2700 and 3300 Angstroms.