Pseudo-Schottky diode

• US 5,818,084 A
• Filed: 05/15/1996
• Issued: 10/06/1998
• Est. Priority Date: 05/15/1996
• Status: Expired due to Term

• Current Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Original Assignee: Siliconix Incorporated (Vishay Intertechnology Incorporated)
• Inventors: Williams, Richard K., Blattner, Robert
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US08/648,334
• Time in Patent Office: 874 Days
• Field of Search: 257/329, 257/330, 257/331, 257/332, 257/334, 257/134, 257/135, 257/143, 257/149, 257/401, 257/341, 257/146
• US Class Current: 257/329
• CPC Class Codes: H01L 27/0727 in combination with diodes, or capacitors or resistors
• CPC Class Codes: H01L 29/7802 Vertical DMOS transistors, i.e. VDMOS transistors
• CPC Class Codes: H01L 29/7803 structurally associated with at least one other device assemblies H01L25/00; integrated circuits H01L27/00
• CPC Class Codes: H01L 29/7813 with trench gate electrode, e.g. UMOS transistors trench gate electrodes per se H01L29/4236
• CPC Class Codes: H01L 29/861 Diodes

Abstract

An N-channel MOSFET is fabricated with its source, body and gate connected together and biased at a positive voltage with respect to its drain. The resulting two-terminal device functions generally in the manner of a diode but has a significantly lower turn-on voltage than a conventional PN diode. The device is therefore referred to as a "pseudo-Schottky diode". Pseudo-Schottky diodes have numerous uses, but they are particularly useful when connected to shunt current from a conventional PN diode or MOSFET and thereby prevent such conditions as snapback and latchup which can result from the storage of minority carriers in a forward-biased PN junction. Also, because the pseudo-Schottky diode is a majority carrier device, the diode recovery time, amount of stored charge, and peak reverse current are much lower than in a conventional PN diode.

Claims

1. A semiconductor device comprising:

a source region of a first conductivity type;

a body region of a second conductivity type opposite to said first conductivity type adjacent said source region;

a drain region of said first conductivity type adjacent said body region; and

a gate separated by an insulating layer from a channel region of said body region,

wherein said source region, said body region and said drain region are formed in a semiconductor chip, said gate being positioned in a trench which is formed at a surface of said chip, said source region, said body region and said gate being shorted together and biased at a first voltage and said drain region being biased at a second voltage, said first and second voltages being established such that a junction between said body and said drain is forward-biased.

2. The semiconductor device of claim 1 wherein said source region and said body region are adjacent a top side of said chip and said drain region is adjacent a back side of said chip.

3. The semiconductor device of claim 1 wherein a thickness of said insulating layer is in the range of 400 Å

to 1000 Å

.

4. A combination including the semiconductor device of claim 1 and a PN diode, said PN diode being connected between said source and drain regions.

5. The combination of claim 4 wherein said diode has an anode and a cathode, wherein said source region is electrically connected with said anode and said drain region is electrically connected with said cathode.

6. The combination of claim 4, said semiconductor device and said PN diode being formed on a single integrated circuit.

7. A combination including the semiconductor device of claim 1 and a transistor, said transistor having a second drain region and a second body region, wherein said source region of said semiconductor device is electrically connected to said second body region and said drain region of said semiconductor device is electrically connected to said second drain region.

8. The combination of claim 7 wherein said semiconductor device and said transistor are formed in said semiconductor chip.

9. A power converter comprising:

a switch and a diode connected in series;

an inductor connected to a common node between said switch and said diode; and

the semiconductor device of claim 1 connected in parallel with said diode.

10. A power converter comprising:

a first MOSFET of a first conductivity type and a second MOSFET of a second conductivity type opposite to said first conductivity type connected in series;

an inductor connected to a common node between said first and second MOSFETs; and

the semiconductor device of claim 1 connected in parallel with said first MOSFET.

11. The power converter of claim 10 further comprising a third MOSFET connected in parallel with said second MOSFET, said third MOSFET having source, body and drain terminals shorted together.

12. A power converter comprising:

an inductor and a switch connected in series;

a diode connected to a common node between said switch and said inductor; and

the semiconductor device of claim 1 connected in parallel with said diode.

13. A current mirror arrangement comprising:

the semiconductor device of claim 1 connected to a supply voltage; and

a MOSFET, a gate of said MOSFET being connected to said gate of said semiconductor device.

14. A semiconductor device formed within a transistor comprising:

a source region of a first conductivity type;

a body region of a second conductivity type adjacent said source region;

a drain region of said first conductivity type adjacent said body region;

a first gate separated by a first insulating layer from a channel region of said body region, and

a second gate separated by a second insulating layer from a channel region of said body region,

wherein said source region, said body region and said second gate are shorted together and biased at a first voltage and said drain region is biased at a second voltage, said first and second voltages being established such that a junction between said body and said drain is forward-biased.